clock.tan.summary

用VHDL实现的完整数字钟代码

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 2.400 ns
From           : S1224
To             : CNT12_24:U2|CQI1[2]
From Clock     : --
To Clock       : SELJ
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 53.300 ns
From           : CNT12_24:U2|CQI1[3]
To             : SEGd[1]
From Clock     : CLK1
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 23.300 ns
From           : S1224
To             : CNT12_24:U2|CQI2[0]
From Clock     : --
To Clock       : CLK1
Failed Paths   : 0

Type           : Clock Setup: 'SELJ'
Slack          : N/A
Required Time  : None
Actual Time    : 33.33 MHz ( period = 30.000 ns )
From           : CNT12_24:U2|CQI2[0]
To             : CNT12_24:U2|CQI1[2]
From Clock     : SELJ
To Clock       : SELJ
Failed Paths   : 0

Type           : Clock Setup: 'CLK1'
Slack          : N/A
Required Time  : None
Actual Time    : 45.05 MHz ( period = 22.200 ns )
From           : CNT12_24:U2|CQI2[0]
To             : CNT12_24:U2|CQI1[2]
From Clock     : CLK1
To Clock       : CLK1
Failed Paths   : 0

Type           : Clock Setup: 'SETM'
Slack          : N/A
Required Time  : None
Actual Time    : 50.76 MHz ( period = 19.700 ns )
From           : CNT12_24:U2|CQI2[0]
To             : CNT12_24:U2|CQI1[2]
From Clock     : SETM
To Clock       : SETM
Failed Paths   : 0

Type           : Clock Setup: 'STEH'
Slack          : N/A
Required Time  : None
Actual Time    : 52.91 MHz ( period = 18.900 ns )
From           : CNT12_24:U2|CQI2[0]
To             : CNT12_24:U2|CQI1[2]
From Clock     : STEH
To Clock       : STEH
Failed Paths   : 0

Type           : Clock Setup: 'CLK1024'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 125.00 MHz ( period = 8.000 ns )
From           : LED:U5|COUNT[0]
To             : LED:U5|COUNT[2]
From Clock     : CLK1024
To Clock       : CLK1024
Failed Paths   : 0

Type           : Clock Hold: 'SELJ'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : CNT12_24:U2|CQI2[1]
To             : CNT12_24:U2|CQI2[1]
From Clock     : SELJ
To Clock       : SELJ
Failed Paths   : 41

Type           : Clock Hold: 'CLK1'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : CNT12_24:U2|CQI2[1]
To             : CNT12_24:U2|CQI2[1]
From Clock     : CLK1
To Clock       : CLK1
Failed Paths   : 21

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 62

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