clock.fit.summary

来自「用VHDL实现的完整数字钟代码」· SUMMARY 代码 · 共 11 行

Fitter Status : Successful - Thu Dec 04 16:54:44 2008
Quartus II Version : 8.0 Build 215 05/29/2008 SJ Web Edition
Revision Name : clock
Top-level Entity Name : clock
Family : FLEX10K
Device : EPF10K20TC144-4
Timing Models : Final
Total logic elements : 86 / 1,152 ( 7 % )
Total pins : 19 / 102 ( 19 % )
Total memory bits : 0 / 12,288 ( 0 % )