clock.vhd

用VHDL实现的完整数字钟代码

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY clock is
PORT(CLK1,CLK1024,CLK2048,SELJ,STEH,SETM,RST,S1224 :IN STD_LOGIC;
                SEGd: OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
                SELd: OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
                 FeM: OUT STD_LOGIC);
END ;
 
ARCHITECTURE one OF clock IS
  COMPONENT CNT60 -------------调用CNT60计数器
 PORT(CLK,RST,EN:IN STD_LOGIC;
        COUT1:  OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
        COUT2:  OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
        CO:    OUT STD_LOGIC);
END COMPONENT ;

  COMPONENT CNT12_24 --------------调用CNT12_24 
   PORT(CLK,RST,EN,set1224:IN STD_LOGIC;
        COUT1:  OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
        COUT2:  OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
        CO:    OUT STD_LOGIC);
   END COMPONENT ;
 
COMPONENT FM -------------调用FM蜂鸣器
 PORT(CLK1024,CLK2048:IN STD_LOGIC;
       FS10: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
       FS1:  IN STD_LOGIC_VECTOR(3 DOWNTO 0);
       FM10:  IN STD_LOGIC_VECTOR(3 DOWNTO 0);
       FM1:  IN STD_LOGIC_VECTOR(3 DOWNTO 0);
       QFM:  OUT STD_LOGIC);
END COMPONENT ;

COMPONENT CONTROL ------------调用CONTROL
 PORT(CLKH,CLKM,JS,QS,QM:IN STD_LOGIC;
        ENH,ENM,CPH,CPM:OUT STD_LOGIC);
END COMPONENT ;

COMPONENT led -------------调用led
 PORT(ADIN :IN STD_LOGIC_VECTOR(23 DOWNTO 0);
      CK:IN STD_LOGIC;
SEG :OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
SEL: OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END COMPONENT ;

SIGNAL CP1,EN1,CP2,EN2,CO2,CO3,ACC:  STD_LOGIC;
SIGNAL HS,HG,MS,MG,SS,SG:        STD_LOGIC_vector(3 downto 0);
SIGNAL MFS,MFG,SFS,SFG:          STD_LOGIC_vector(3 downto 0);
BEGIN
 ACC<='1';
U1: CONTROL PORT MAP(JS=>SELJ,CLKH=>STEH,CLKM=>SETM,QS=>CO3,QM=>CO2,CPH=>CP1,CPM=>CP2,ENH=>EN1,ENM=>EN2); 
U2: CNT12_24 PORT MAP(SET1224=>S1224,CLK=>CP1,EN=>EN1,RST=>RST,COUT2=>HS,COUT1=>HG);
U3: CNT60 PORT MAP(CLK=>CP2,EN=>EN2,RST=>RST,COUT2=>MS,COUT1=>MG,CO=>CO2);
U4: CNT60 PORT MAP(en=>ACC,CO=>CO3,RST=>RST,Clk=>CLK1,COUT2=>SS,COUT1=>SG);
U5: 	LED PORT MAP(ck=>clk1024,ADIN(23 DOWNTO 20)=>HS,ADIN(19 DOWNTO 16)=>HG,ADIN(15 DOWNTO 12)=>MS,ADIN(11 DOWNTO 8)=>MG,ADIN(7 DOWNTO 4)=>SS,ADIN(3 DOWNTO 0)=>SG,SEG=>SEGD,SEL=>SELD);
U6: FM PORT MAP(FS10=>MFS,FS1=>MFG,FM10=>SFS,FM1=>SFG,CLK1024=>CLK1024,CLK2048=>CLK2048,QFM=>FeM);

END ;