cnt60.vhd

用VHDL实现的完整数字钟代码

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT60 IS
PORT(CLK,RST,EN:IN STD_LOGIC;
        COUT1:  OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
        COUT2:  OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
           CO:  OUT STD_LOGIC);
END  CNT60;
 
ARCHITECTURE one OF  CNT60 IS
BEGIN
PROCESS(CLK,RST,EN)
VARIABLE CQI1:  STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE CQI2: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
 IF RST='1' THEN CQI1:=(OTHERS=>'0');  CQI2:=(OTHERS=>'0');
 ELSIF CLK'EVENT AND CLK='1' THEN
   IF EN='1' THEN
       IF CQI1=9 THEN 
           CQI1:=(OTHERS=>'0');
           IF CQI2=5 THEN CQI2:=(OTHERS=>'0');
           ELSE   CQI2:=CQI2+1;
           END IF;
        ELSE   CQI1:=CQI1+1;
        END IF;
     END IF;
  END IF;
 IF CQI1=9 AND CQI2=5 THEN CO<='1';
  ELSE CO<='0';
 END IF;
COUT1<=CQI1;
COUT2<=CQI2;
END PROCeSS;
END ;