clkdiv.vhd

vhdl实现任意分频

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY clkdiv IS
PORT(
 CLK: IN STD_LOGIC;
 CLKOUT_3:BUFFER STD_LOGIC
);
END clkdiv;

ARCHITECTURE A OF clkdiv IS
 CONSTANT n:INTEGER:=26;
 SIGNAL CNT1,CNT2:integer:=0;
 SIGNAL OUTTEMP:STD_LOGIC;
 SIGNAL LOUT:STD_LOGIC;
 SIGNAL OUT3:STD_LOGIC:='0';

 BEGIN
 l1:  PROCESS(CLK)
  BEGIN
  IF CLK'EVENT AND CLK='1'THEN
   IF CNT1=n-1 THEN
    CNT1<=0;
   ELSE
    CNT1<=CNT1+1;
   END IF;
  END IF;
 END PROCESS;
 
 l2: PROCESS(CLK)
  BEGIN
  IF CLK'EVENT AND CLK='0'THEN
   IF CNT2=n-1 THEN
    CNT2<=0;
   ELSE 
    CNT2<=CNT2+1;
   END IF;
  END IF;
 END PROCESS;

 l3: PROCESS(CNT1,CNT2 )
  BEGIN
  if ((n mod 2)=1) then
   IF CNT1=1 THEN
    IF CNT2=0 THEN
     OUTTEMP<='1';
    ELSE OUTTEMP<='0';
    END IF;
   ELSIF CNT1=(n+1)/2 THEN
    IF CNT2=(n+1)/2 THEN
     OUTTEMP<='1';
    ELSE OUTTEMP<='0';
    END IF;
   ELSE 
    OUTTEMP<='0';
   END IF;
  else
   if cnt1=1 then
    outtemp<='1';
   elsif (cnt1=(n/2+1)) then
    outtemp<='1';
   else
    outtemp<='0';
   end if;
  end if;
 END PROCESS;
 
 l4:  PROCESS(OUTTEMP,clk)
  BEGIN
  if ((n/=2) and (n/=1)) then
   IF OUTTEMP'EVENT AND OUTTEMP='1' THEN
    CLKOUT_3<=NOT CLKOUT_3;
   END IF;
  elsif (n=2) then
   if(clk'event and clk='1')then
    clkout_3<=not clkout_3;
   end if;
  else
   clkout_3<=clk;
  end if;
 END PROCESS;
END A;