四级流水线四位乘法器.txt

流水线乘法器与加法器 开发环境：Modelsim（verilog hdl）

module mult(clk,reset,a,b,product,reg1,reg2,reg3);
input clk;
input reset;
input[3:0] a,b;
output[7:0] product;
output[10:0] reg1;
output[11:0] reg2;
output[11:0] reg3;

reg[10:0] reg1;
reg[11:0] reg2;
reg[11:0] reg3;
reg[7:0] product;

always@(posedge clk or posedge reset)
  begin
    if(reset)
      reg1<=11'd0;
    else
      begin
        reg1[3:0]<=b[0]?a:4'b0;
        reg1[7:4]<=a;
        reg1[10:8]<=b[3:1];
      end
  end

always@(posedge clk or posedge reset)
  begin
    if(reset)
      reg2<=12'd0;
    else
      begin
        reg2[5:0]<=reg1[8]?(reg1[3:0]+{a,1'b0}):{2'b0,reg1[3:0]};
        reg2[9:6]<=reg1[7:4];
        reg2[11:10]<=reg1[10:9];
      end
  end

always@(posedge clk or posedge reset)
  begin
    if(reset)
      reg3<=12'd0;
    else
      begin
        reg3[6:0]<=reg2[10]?(reg2[5:0]+{a,2'b0}):{1'b0,reg2[5:0]};
        reg3[10:7]<=reg2[9:6];
        reg3[11]<=reg2[11];
      end
  end

always@(posedge clk or posedge reset)
  begin
    if(reset)
      product<=8'd0;
    else
      begin
        product[7:0]<=reg3[11]?(reg3[6:0]+{a,3'b0}):{1'b0,reg3[6:0]};
      end
  end

endmodule