四级流水线四位加法器.txt

来自「流水线乘法器与加法器 开发环境：Modelsim（verilog hdl）」· 文本 代码 · 共 66 行

module adder(clk,reset,a,b,sum,c);
input clk;
input reset;
input[3:0] a,b;
output[3:0] sum;
output c;

reg[7:0] reg1;
reg[6:0] reg2;
reg[5:0] reg3;
reg[3:0] sum;
reg c;

always@(posedge clk or posedge reset)
  begin
    if(reset)
      reg1<=8'd0;
    else
      begin
        reg1[1:0]<=a[0]+b[0];
        reg1[7:2]<={b[3],a[3],b[2],a[2],b[1],a[1]};
      end
  end

always@(posedge clk or posedge reset)
  begin
    if(reset)
      reg2<=7'd0;
    else
      begin
        reg2[0]<=reg1[0];
        reg2[2:1]<=reg1[1]+reg1[2]+reg1[3];
        reg2[6:3]<=reg1[7:4];
      end
  end

always@(posedge clk or posedge reset)
  begin
    if(reset)
      reg3<=6'd0;
    else
      begin
        reg3[1:0]<=reg2[1:0];
        reg3[3:2]<=reg2[2]+reg2[3]+reg2[4];
        reg3[5:4]<=reg2[6:5];
      end
  end

always@(posedge clk or posedge reset)
  begin
    if(reset)
      begin
        sum<=4'd0;
        c<=1'd0;
      end
    else
      begin
        sum[2:0]<=reg3[2:0];
        {c,sum[3]}<={reg3[3]+reg3[4]+reg3[5]};
      end
  end

endmodule