lab4.tan.summary

利用FPGA做出十进制加减法！带有进位借位显示

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 5.036 ns
From           : EN
To             : CO~reg0
From Clock     : --
To Clock       : CLK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 13.883 ns
From           : CO~reg0
To             : CO
From Clock     : CLK
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 3.543 ns
From           : CLR
To             : CO~reg0
From Clock     : --
To Clock       : CLK
Failed Paths   : 0

Type           : Clock Setup: 'CLK'
Slack          : N/A
Required Time  : None
Actual Time    : 233.43 MHz ( period = 4.284 ns )
From           : Y1[0]
To             : CO~reg0
From Clock     : CLK
To Clock       : CLK
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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