lab4.vhd

来自「利用FPGA做出十进制加减法！带有进位借位显示」· VHDL 代码 · 共 34 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.ALL;

entity lab4 is
  port(CLR,EN,CTRL,CLK:IN STD_LOGIC;
		            CO:OUT STD_LOGIC;
					 Y:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
		);
END lab4;

ARCHITECTURE ONE OF lab4 is
begin 
 process(CLR,EN,CTRL,CLK)
  VARIABLE Y1:STD_LOGIC_VECTOR(3 DOWNTO 0);
  BEGIN
  IF CLR='0' THEN Y1:=(OTHERS=>'0'); CO<='0';
    ELSIF CLK'EVENT AND CLK='1' THEN
        IF CLR='1' AND EN='1' AND CTRL='1' THEN
           IF Y1 < 9 THEN 
              CO <='0';Y1:=Y1+1;
           ELSE CO<='1';Y1:=(OTHERS=>'0');
           END IF;
        END IF;
        IF CLR='1' AND EN='1' AND CTRL='0' THEN
           IF Y1>0 THEN CO<='0';Y1:=Y1-1;
           ELSE CO<='1';Y1:="1001";
           END IF;
        END IF;
    ELSIF EN='0' THEN Y1:=Y1;
  END IF;
  Y<=Y1;
 END PROCESS;
END;