📄 vregsw.psm
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;;============================================================================
;; Copyright (c) 2007 Xilinx, Inc.
;; This design is confidential and proprietary of Xilinx, All Rights Reserved.
;;============================================================================
;; ____ ____
;; / /\/ /
;; /___/ \ / Vendor: Xilinx
;; \ \ \/ Version: 1.0.0
;; \ \ Filename: vregsw.psm
;; / / Date Created: July 1, 2007
;; /___/ /\ Last Modified: July 1, 2007
;; \ \ / \
;; \___\/\___\
;;
;; Devices: Spartan-3 Generation FPGA
;; Purpose: Voltage regulator control program
;; Contact: crabill@xilinx.com
;; Reference: Borrowed heavily from Spartan-3A Starter Kit
;;
;; Revision History:
;; Rev 1.0.0 - (crabill) First created July 1, 2007.
;;
;;============================================================================
;;
;; LIMITED WARRANTY AND DISCLAIMER. These designs are provided to you "as is".
;; Xilinx and its licensors make and you receive no warranties or conditions,
;; express, implied, statutory or otherwise, and Xilinx specifically disclaims
;; any implied warranties of merchantability, non-infringement, or fitness for
;; a particular purpose. Xilinx does not warrant that the functions contained
;; in these designs will meet your requirements, or that the operation of
;; these designs will be uninterrupted or error free, or that defects in the
;; designs will be corrected. Furthermore, Xilinx does not warrant or make any
;; representations regarding use or the results of the use of the designs in
;; terms of correctness, accuracy, reliability, or otherwise.
;;
;; LIMITATION OF LIABILITY. In no event will Xilinx or its licensors be liable
;; for any loss of data, lost profits, cost or procurement of substitute goods
;; or services, or for any special, incidental, consequential, or indirect
;; damages arising from the use or operation of the designs or accompanying
;; documentation, however caused and on any theory of liability. This
;; limitation will apply even if Xilinx has been advised of the possibility
;; of such damage. This limitation shall apply not-withstanding the failure
;; of the essential purpose of any limited remedies herein.
;;
;;============================================================================
;; Copyright (c) 2007 Xilinx, Inc.
;; This design is confidential and proprietary of Xilinx, All Rights Reserved.
;;============================================================================
CONSTANT rs232dce_data , 00 ; port for data read and write
CONSTANT rs232dce_txfull , 01 ; read lsb to sense tx fifo full
CONSTANT rs232dce_rxpres , 02 ; read lsb to sense rx fifo pres
CONSTANT i2c_select , 18 ; port for i2c device select
CONSTANT i2c_select_none , 00 ; select nothing
CONSTANT i2c_select_reg1 , 01 ; regulator 1
CONSTANT i2c_select_reg2 , 02 ; regulator 2
CONSTANT i2c_sdascl , 19 ; control port for sda and scl
CONSTANT i2c_sdascl_init , 03 ; default state, pull high
CONSTANT i2c_sdascl_sscl , 01 ; set scl by logical or
CONSTANT i2c_sdascl_cscl , FE ; clear scl by logical and
CONSTANT i2c_sdascl_ssda , 02 ; set sda by logical or
CONSTANT i2c_sdascl_csda , FD ; clear sda by logical and
CONSTANT i2c_lines , 00 ; scratchpad for i2c line state
CONSTANT reg_addr_wr , C0 ; regulator address, write
CONSTANT reg_addr_rd , C1 ; regulator address, read
CONSTANT reg_select , 01 ; scratchpad for selected reg
CONSTANT reg_select_port , 02 ; scratchpad for selected reg port
CONSTANT reg_select_addr , 03 ; scratchpad for selected reg addr
CONSTANT zero , 00 ; zero
CONSTANT false , 00 ; false
CONSTANT one , 01 ; one
CONSTANT true , 01 ; true
;; Define constants for all the ascii values.
CONSTANT ascii_BS , 08 ; ascii code (backspace)
CONSTANT ascii_LF , 0A ; ascii code (line feed)
CONSTANT ascii_CR , 0D ; ascii code (carriage return)
CONSTANT ascii_SPACE , 20 ; ascii code
CONSTANT ascii_EXCLAIM , 21 ; ascii code
CONSTANT ascii_DBLQUOT , 22 ; ascii code
CONSTANT ascii_NUMSIGN , 23 ; ascii code
CONSTANT ascii_DOLLAR , 24 ; ascii code
CONSTANT ascii_PERCENT , 25 ; ascii code
CONSTANT ascii_AMP , 26 ; ascii code
CONSTANT ascii_SINQUOT , 27 ; ascii code
CONSTANT ascii_LPAREN , 28 ; ascii code
CONSTANT ascii_RPAREN , 29 ; ascii code
CONSTANT ascii_ASTERISK , 2A ; ascii code
CONSTANT ascii_PLUS , 2B ; ascii code
CONSTANT ascii_COMMA , 2C ; ascii code
CONSTANT ascii_MINUS , 2D ; ascii code
CONSTANT ascii_PERIOD , 2E ; ascii code
CONSTANT ascii_FWDSLASH , 2F ; ascii code
CONSTANT ascii_0 , 30 ; ascii code
CONSTANT ascii_1 , 31 ; ascii code
CONSTANT ascii_2 , 32 ; ascii code
CONSTANT ascii_3 , 33 ; ascii code
CONSTANT ascii_4 , 34 ; ascii code
CONSTANT ascii_5 , 35 ; ascii code
CONSTANT ascii_6 , 36 ; ascii code
CONSTANT ascii_7 , 37 ; ascii code
CONSTANT ascii_8 , 38 ; ascii code
CONSTANT ascii_9 , 39 ; ascii code
CONSTANT ascii_COLON , 3A ; ascii code
CONSTANT ascii_SEMI , 3B ; ascii code
CONSTANT ascii_LESS , 3C ; ascii code
CONSTANT ascii_EQUAL , 3D ; ascii code
CONSTANT ascii_GREATER , 3E ; ascii code
CONSTANT ascii_QUESTION , 3F ; ascii code
CONSTANT ascii_CIRCAT , 40 ; ascii code
CONSTANT ascii_A , 41 ; ascii code
CONSTANT ascii_B , 42 ; ascii code
CONSTANT ascii_C , 43 ; ascii code
CONSTANT ascii_D , 44 ; ascii code
CONSTANT ascii_E , 45 ; ascii code
CONSTANT ascii_F , 46 ; ascii code
CONSTANT ascii_G , 47 ; ascii code
CONSTANT ascii_H , 48 ; ascii code
CONSTANT ascii_I , 49 ; ascii code
CONSTANT ascii_J , 4A ; ascii code
CONSTANT ascii_K , 4B ; ascii code
CONSTANT ascii_L , 4C ; ascii code
CONSTANT ascii_M , 4D ; ascii code
CONSTANT ascii_N , 4E ; ascii code
CONSTANT ascii_O , 4F ; ascii code
CONSTANT ascii_P , 50 ; ascii code
CONSTANT ascii_Q , 51 ; ascii code
CONSTANT ascii_R , 52 ; ascii code
CONSTANT ascii_S , 53 ; ascii code
CONSTANT ascii_T , 54 ; ascii code
CONSTANT ascii_U , 55 ; ascii code
CONSTANT ascii_V , 56 ; ascii code
CONSTANT ascii_W , 57 ; ascii code
CONSTANT ascii_X , 58 ; ascii code
CONSTANT ascii_Y , 59 ; ascii code
CONSTANT ascii_Z , 5A ; ascii code
CONSTANT ascii_LBKT , 5B ; ascii code
CONSTANT ascii_BKSLASH , 5C ; ascii code
CONSTANT ascii_RBKT , 5D ; ascii code
CONSTANT ascii_CARET , 5E ; ascii code
CONSTANT ascii_DASH , 5F ; ascii code
CONSTANT ascii_TICK , 60 ; ascii code
CONSTANT ascii_a , 61 ; ascii code
CONSTANT ascii_b , 62 ; ascii code
CONSTANT ascii_c , 63 ; ascii code
CONSTANT ascii_d , 64 ; ascii code
CONSTANT ascii_e , 65 ; ascii code
CONSTANT ascii_f , 66 ; ascii code
CONSTANT ascii_g , 67 ; ascii code
CONSTANT ascii_h , 68 ; ascii code
CONSTANT ascii_i , 69 ; ascii code
CONSTANT ascii_j , 6A ; ascii code
CONSTANT ascii_k , 6B ; ascii code
CONSTANT ascii_l , 6C ; ascii code
CONSTANT ascii_m , 6D ; ascii code
CONSTANT ascii_n , 6E ; ascii code
CONSTANT ascii_o , 6F ; ascii code
CONSTANT ascii_p , 70 ; ascii code
CONSTANT ascii_q , 71 ; ascii code
CONSTANT ascii_r , 72 ; ascii code
CONSTANT ascii_s , 73 ; ascii code
CONSTANT ascii_t , 74 ; ascii code
CONSTANT ascii_u , 75 ; ascii code
CONSTANT ascii_v , 76 ; ascii code
CONSTANT ascii_w , 77 ; ascii code
CONSTANT ascii_x , 78 ; ascii code
CONSTANT ascii_y , 79 ; ascii code
CONSTANT ascii_z , 7A ; ascii code
CONSTANT ascii_LBRACE , 7B ; ascii code
CONSTANT ascii_VBAR , 7C ; ascii code
CONSTANT ascii_RBRACE , 7D ; ascii code
CONSTANT ascii_TILDE , 7E ; ascii code
CONSTANT ascii_ULINE , 7F ; ascii code
;; Constant to define a software delay of 1us. This must be adjusted
;; to reflect the clock period. Every instruction executes in 2 cycles.
;; delay_1us_constant = (clock_rate - 6)/4, where 'clock_rate' is in
;; MHz. Example: For 50MHz clock the constant value is (50-6)/4 = 11.
;; For clock rates below 10MHz the value of 1 must be used and the
;; operation will become slower than intended.
CONSTANT delay_1us_const , 0B ; delay 1 us value
;;============================================================================
;; Infinite loop.
;;============================================================================
cold_start: CALL i2c_initialize
LOAD s0, 00
STORE s0, reg_select
LOAD s0, 01
STORE s0, reg_select_port
LOAD s0, 39
STORE s0, reg_select_addr
CALL buck_ramp_on
CALL welcome_message
main_loop: CALL rx_fm_dce
COMPARE s0, ascii_1
CALL Z, select_reg
COMPARE s0, ascii_2
CALL Z, select_reg
COMPARE s0, ascii_3
CALL Z, select_reg
COMPARE s0, ascii_4
CALL Z, select_reg
COMPARE s0, ascii_5
CALL Z, select_reg
COMPARE s0, ascii_6
CALL Z, select_reg
COMPARE s0, ascii_7
CALL Z, select_reg
COMPARE s0, ascii_8
CALL Z, select_reg
COMPARE s0, ascii_P
CALL Z, dump_selected
COMPARE s0, ascii_PLUS
CALL Z, bump_up
COMPARE s0, ascii_MINUS
CALL Z, bump_dn
;; Pre-set test matrix on keyboard using keys:
;;
;; Q W E
;; A S D
;; Z X C
;;
;; FPGA_H,DDR2_L FPGA_H,DDR2_N FPGA_H,DDR2_H
;; FPGA_N,DDR2_L FPGA_N,DDR2_N FPGA_N,DDR2_H
;; FPGA_L,DDR2_L FPGA_L,DDR2_N FPGA_L,DDR2_H
COMPARE s0, ascii_Q
CALL Z, fpga_h_ddr2_l
COMPARE s0, ascii_W
CALL Z, fpga_h_ddr2_n
COMPARE s0, ascii_E
CALL Z, fpga_h_ddr2_h
COMPARE s0, ascii_A
CALL Z, fpga_n_ddr2_l
COMPARE s0, ascii_S
CALL Z, fpga_n_ddr2_n
COMPARE s0, ascii_D
CALL Z, fpga_n_ddr2_h
COMPARE s0, ascii_Z
CALL Z, fpga_l_ddr2_l
COMPARE s0, ascii_X
CALL Z, fpga_l_ddr2_n
COMPARE s0, ascii_C
CALL Z, fpga_l_ddr2_h
JUMP main_loop
;;============================================================================
;; Regulator adjust routines.
;;============================================================================
select_reg: SUB s0, 31
STORE s0, reg_select
TEST s0, 04
JUMP Z, use_port_one
JUMP use_port_two
use_port_one: LOAD s1, 01
STORE s1, reg_select_port
JUMP calc_addr
use_port_two: LOAD s1, 02
STORE s1, reg_select_port
JUMP calc_addr
calc_addr: FETCH s0, reg_select
AND s0, 03
LOAD s1, 39
COMPARE s0, 00
JUMP Z, store_addr
LOAD s1, 3A
COMPARE s0, 01
JUMP Z, store_addr
LOAD s1, 23
COMPARE s0, 02
JUMP Z, store_addr
LOAD s1, 29
COMPARE s0, 03
JUMP Z, store_addr
LOAD s1, 11
store_addr: STORE s1, reg_select_addr
CALL print_selected
CALL dump_selected
LOAD s0, 00
RETURN
print_selected: FETCH s2, reg_select
COMPARE s2, 00
CALL Z, print1
COMPARE s2, 01
CALL Z, print2
COMPARE s2, 02
CALL Z, print3
COMPARE s2, 03
CALL Z, print4
COMPARE s2, 04
CALL Z, print5
COMPARE s2, 05
CALL Z, print6
COMPARE s2, 06
CALL Z, print7
COMPARE s2, 07
CALL Z, print8
RETURN
dump_selected: CALL print_rg
CALL read_selected
LOAD s0, s2
CALL print_s0
LOAD s0, ascii_CR
CALL tx_to_dce
LOAD s0, ascii_CR
CALL tx_to_dce
LOAD s0, 00
RETURN
read_selected: FETCH s4, reg_select_port
OUTPUT s4, i2c_select
FETCH s4, reg_select_addr
CALL i2c_start
LOAD s2, reg_addr_wr
CALL i2c_tx_byte
CALL i2c_rx_ack
LOAD s2, s4
CALL i2c_tx_byte
CALL i2c_rx_ack
CALL i2c_start
LOAD s2, reg_addr_rd
CALL i2c_tx_byte
CALL i2c_rx_ack
CALL i2c_rx_byte
CALL i2c_tx_noack
CALL i2c_stop
CALL i2c_select_off
RETURN
bump_up: CALL read_selected
LOAD s5, s2
ADD s5, 01
CALL write_selected
CALL dump_selected
LOAD s0, 00
RETURN
bump_dn: CALL read_selected
LOAD s5, s2
SUB s5, 01
CALL write_selected
CALL dump_selected
LOAD s0, 00
RETURN
write_selected: FETCH s4, reg_select_port
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