vregsw.psm

来自「verilog语言 vga 控制 和显示功能」· PSM 代码 · 共 1,115 行 · 第 1/3 页

                  OUTPUT s4, i2c_select
                  FETCH s4, reg_select_addr
                  CALL i2c_start
                  LOAD s2, reg_addr_wr
                  CALL i2c_tx_byte
                  CALL i2c_rx_ack
                  LOAD s2, s4
                  CALL i2c_tx_byte
                  CALL i2c_rx_ack
                  LOAD s2, s5
                  CALL i2c_tx_byte
                  CALL i2c_rx_ack
                  CALL i2c_stop
                  CALL i2c_select_off
                  RETURN

    buck_ramp_on: LOAD s4, i2c_select_reg1
                  OUTPUT s4, i2c_select
                  CALL buck_trend
                  LOAD s4, i2c_select_reg2
                  OUTPUT s4, i2c_select
                  CALL buck_trend
                  RETURN
      buck_trend: CALL i2c_start
                  LOAD s2, reg_addr_wr
                  CALL i2c_tx_byte
                  CALL i2c_rx_ack
                  LOAD s2, 20
                  CALL i2c_tx_byte
                  CALL i2c_rx_ack
                  LOAD s2, 11
                  CALL i2c_tx_byte
                  CALL i2c_rx_ack
                  CALL i2c_stop
                  CALL i2c_select_off
                  RETURN

;;============================================================================
;; Specific test scenarios.
;;============================================================================

   fpga_h_ddr2_l: CALL fpga_h
                  CALL ddr2_l
                  CALL message_t
                  LOAD s0, 00
                  RETURN

   fpga_h_ddr2_n: CALL fpga_h
                  CALL ddr2_n
                  CALL message_t
                  LOAD s0, 00
                  RETURN

   fpga_h_ddr2_h: CALL fpga_h
                  CALL ddr2_h
                  CALL message_t
                  LOAD s0, 00
                  RETURN

   fpga_n_ddr2_l: CALL fpga_n
                  CALL ddr2_l
                  CALL message_t
                  LOAD s0, 00
                  RETURN

   fpga_n_ddr2_n: CALL fpga_n
                  CALL ddr2_n
                  CALL message_t
                  LOAD s0, 00
                  RETURN

   fpga_n_ddr2_h: CALL fpga_n
                  CALL ddr2_h
                  CALL message_t
                  LOAD s0, 00
                  RETURN

   fpga_l_ddr2_l: CALL fpga_l
                  CALL ddr2_l
                  CALL message_t
                  LOAD s0, 00
                  RETURN

   fpga_l_ddr2_n: CALL fpga_l
                  CALL ddr2_n
                  CALL message_t
                  LOAD s0, 00
                  RETURN

   fpga_l_ddr2_h: CALL fpga_l
                  CALL ddr2_h
                  CALL message_t
                  LOAD s0, 00
                  RETURN

          fpga_l: LOAD s4, i2c_select_reg1
                  OUTPUT s4, i2c_select
                  LOAD s4, 39
                  LOAD s5, 15
                  CALL do_write
                  LOAD s4, 3A
                  LOAD s5, 08
                  CALL do_write
                  LOAD s4, 23
                  LOAD s5, 08
                  CALL do_write
                  LOAD s4, 29
                  LOAD s5, 17
                  CALL do_write
                  CALL i2c_select_off
                  CALL message_f
                  CALL message_l
                  RETURN

          fpga_n: LOAD s4, i2c_select_reg1
                  OUTPUT s4, i2c_select
                  LOAD s4, 39
                  LOAD s5, 17
                  CALL do_write
                  LOAD s4, 3A
                  LOAD s5, 08
                  CALL do_write
                  LOAD s4, 23
                  LOAD s5, 09
                  CALL do_write
                  LOAD s4, 29
                  LOAD s5, 17
                  CALL do_write
                  CALL i2c_select_off
                  CALL message_f
                  CALL message_n
                  RETURN

          fpga_h: LOAD s4, i2c_select_reg1
                  OUTPUT s4, i2c_select
                  LOAD s4, 39
                  LOAD s5, 19
                  CALL do_write
                  LOAD s4, 3A
                  LOAD s5, 08
                  CALL do_write
                  LOAD s4, 23
                  LOAD s5, 0A
                  CALL do_write
                  LOAD s4, 29
                  LOAD s5, 17
                  CALL do_write
                  CALL i2c_select_off
                  CALL message_f
                  CALL message_h
                  RETURN

          ddr2_l: LOAD s4, i2c_select_reg2
                  OUTPUT s4, i2c_select
                  LOAD s4, 39
                  LOAD s5, 17
                  CALL do_write
                  LOAD s4, 3A
                  LOAD s5, 07
                  CALL do_write
                  LOAD s4, 23
                  LOAD s5, 02
                  CALL do_write
                  LOAD s4, 29
                  LOAD s5, 08
                  CALL do_write
                  CALL i2c_select_off
                  CALL message_d
                  CALL message_l
                  RETURN

          ddr2_n: LOAD s4, i2c_select_reg2
                  OUTPUT s4, i2c_select
                  LOAD s4, 39
                  LOAD s5, 17
                  CALL do_write
                  LOAD s4, 3A
                  LOAD s5, 08
                  CALL do_write
                  LOAD s4, 23
                  LOAD s5, 03
                  CALL do_write
                  LOAD s4, 29
                  LOAD s5, 09
                  CALL do_write
                  CALL i2c_select_off
                  CALL message_d
                  CALL message_n
                  RETURN

          ddr2_h: LOAD s4, i2c_select_reg2
                  OUTPUT s4, i2c_select
                  LOAD s4, 39
                  LOAD s5, 17
                  CALL do_write
                  LOAD s4, 3A
                  LOAD s5, 09
                  CALL do_write
                  LOAD s4, 23
                  LOAD s5, 04
                  CALL do_write
                  LOAD s4, 29
                  LOAD s5, 0A
                  CALL do_write
                  CALL i2c_select_off
                  CALL message_d
                  CALL message_h
                  RETURN

        do_write: CALL i2c_start
                  LOAD s2, reg_addr_wr
                  CALL i2c_tx_byte
                  CALL i2c_rx_ack
                  LOAD s2, s4
                  CALL i2c_tx_byte
                  CALL i2c_rx_ack
                  LOAD s2, s5
                  CALL i2c_tx_byte
                  CALL i2c_rx_ack
                  CALL i2c_stop
                  RETURN

;;============================================================================
;; Routines for serial transmission.  These use s0 for parameter passing
;; and return, and use s1 as scratch for temporary storage.  Note that
;; these may block execution for considerable time depending on fifo state.
;;============================================================================

       tx_to_dce: INPUT s1, rs232dce_txfull           ; obtain fifo status
                  TEST s1, true                       ; check txfull true
                  JUMP NZ, tx_to_dce                  ; if full, sit and spin
                  OUTPUT s0, rs232dce_data            ; write data to fifo
                  RETURN                              ; all done

       rx_fm_dce: INPUT s1, rs232dce_rxpres           ; obtain fifo status
                  TEST s1, true                       ; check rxpres true
                  JUMP Z, rx_fm_dce                   ; if empty, sit and spin
                  INPUT s0, rs232dce_data             ; read data from fifo
                  RETURN                              ; all done

        print_s0: LOAD s2, s0                         ; save a nice copy
                  SR0 s0                              ; shift high nibble
                  SR0 s0                              ; into low position
                  SR0 s0                              ; and mask high part
                  SR0 s0                              ; in the process
                  SUB s0, 0A                          ; test if digits
                  JUMP C, num1                        ; if so, jump adjust
                  ADD s0, 07                          ; ASCII A to F is 41 to 46
            num1: ADD s0, 3A                          ; ASCII 0 to 9 is 30 to 40
                  CALL tx_to_dce                      ; print it out
                  LOAD s0, s2                         ; get the nice copy
                  AND s0, 0F                          ; get rid of msb junk
                  SUB s0, 0A                          ; test if digits
                  JUMP C, num2                        ; if so, jump adjust
                  ADD s0, 07                          ; ASCII A to F is 41 to 46
            num2: ADD s0, 3A                          ; ASCII 0 to 9 is 30 to 40
                  CALL tx_to_dce                      ; print it out
                  LOAD s0, s2                         ; like we found it...
                  RETURN

;;============================================================================
;; Routines to send out messages on the rs232 dce port.
;;============================================================================

 welcome_message: LOAD s0, ascii_CR
                  CALL tx_to_dce
                  LOAD s0, ascii_CR
                  CALL tx_to_dce
                  LOAD s0, ascii_CR
                  CALL tx_to_dce
                  LOAD s0, ascii_R
                  CALL tx_to_dce
                  LOAD s0, ascii_S
                  CALL tx_to_dce
                  LOAD s0, ascii_2
                  CALL tx_to_dce
                  LOAD s0, ascii_3
                  CALL tx_to_dce
                  LOAD s0, ascii_2
                  CALL tx_to_dce
                  LOAD s0, ascii_SPACE
                  CALL tx_to_dce
                  LOAD s0, ascii_V
                  CALL tx_to_dce
                  LOAD s0, ascii_R
                  CALL tx_to_dce
                  LOAD s0, ascii_E
                  CALL tx_to_dce
                  LOAD s0, ascii_G
                  CALL tx_to_dce
                  LOAD s0, ascii_SPACE
                  CALL tx_to_dce
                  LOAD s0, ascii_C
                  CALL tx_to_dce
                  LOAD s0, ascii_o
                  CALL tx_to_dce
                  LOAD s0, ascii_n
                  CALL tx_to_dce
                  LOAD s0, ascii_t
                  CALL tx_to_dce
                  LOAD s0, ascii_r
                  CALL tx_to_dce
                  LOAD s0, ascii_o
                  CALL tx_to_dce
                  LOAD s0, ascii_l
                  CALL tx_to_dce
                  LOAD s0, ascii_CR
                  CALL tx_to_dce

                  LOAD s0, ascii_W
                  CALL tx_to_dce
                  LOAD s0, ascii_A
                  CALL tx_to_dce
                  LOAD s0, ascii_R
                  CALL tx_to_dce
                  LOAD s0, ascii_N
                  CALL tx_to_dce
                  LOAD s0, ascii_I
                  CALL tx_to_dce
                  LOAD s0, ascii_N
                  CALL tx_to_dce
                  LOAD s0, ascii_G
                  CALL tx_to_dce
                  LOAD s0, ascii_COLON
                  CALL tx_to_dce
                  LOAD s0, ascii_SPACE
                  CALL tx_to_dce
                  LOAD s0, ascii_I
                  CALL tx_to_dce
                  LOAD s0, ascii_M
                  CALL tx_to_dce
                  LOAD s0, ascii_P
                  CALL tx_to_dce
                  LOAD s0, ascii_R
                  CALL tx_to_dce
                  LOAD s0, ascii_O
                  CALL tx_to_dce
                  LOAD s0, ascii_P
                  CALL tx_to_dce
                  LOAD s0, ascii_E
                  CALL tx_to_dce
                  LOAD s0, ascii_R
                  CALL tx_to_dce
                  LOAD s0, ascii_SPACE
                  CALL tx_to_dce
                  LOAD s0, ascii_U
                  CALL tx_to_dce
                  LOAD s0, ascii_S
                  CALL tx_to_dce
                  LOAD s0, ascii_E
                  CALL tx_to_dce
                  LOAD s0, ascii_SPACE
                  CALL tx_to_dce
                  LOAD s0, ascii_M
                  CALL tx_to_dce
                  LOAD s0, ascii_A
                  CALL tx_to_dce
                  LOAD s0, ascii_Y
                  CALL tx_to_dce
                  LOAD s0, ascii_SPACE
                  CALL tx_to_dce
                  LOAD s0, ascii_D
                  CALL tx_to_dce
                  LOAD s0, ascii_A
                  CALL tx_to_dce
                  LOAD s0, ascii_M
                  CALL tx_to_dce
                  LOAD s0, ascii_A
                  CALL tx_to_dce
                  LOAD s0, ascii_G
                  CALL tx_to_dce
                  LOAD s0, ascii_E