📄 count_deng.tan.qmsg
字号:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register q\[0\] register q\[2\] 76.92 MHz 13.0 ns Internal " "Info: Clock clk has Internal fmax of 76.92 MHz between source register q\[0\] and destination register q\[2\] (period= 13.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest register register " "Info: + Longest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q\[0\] 1 REG LC3 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3; Fanout = 5; REG Node = 'q\[0\]'" { } { { "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" "" "" { Report "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" Compiler "count_deng" "UNKNOWN" "V1" "D:/第三周 试验 07607邓习海/db/count_deng.quartus_db" { Floorplan "" "" "" { q[0] } "NODE_NAME" } } } { "D:/第三周 试验 07607邓习海/count_deng.vhd" "" "" { Text "D:/第三周 试验 07607邓习海/count_deng.vhd" 21 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns q\[2\] 2 REG LC6 6 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC6; Fanout = 6; REG Node = 'q\[2\]'" { } { { "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" "" "" { Report "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" Compiler "count_deng" "UNKNOWN" "V1" "D:/第三周 试验 07607邓习海/db/count_deng.quartus_db" { Floorplan "" "" "8.000 ns" { q[0] q[2] } "NODE_NAME" } } } { "D:/第三周 试验 07607邓习海/count_deng.vhd" "" "" { Text "D:/第三周 试验 07607邓习海/count_deng.vhd" 21 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns 75.00 % " "Info: Total cell delay = 6.000 ns ( 75.00 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 25.00 % " "Info: Total interconnect delay = 2.000 ns ( 25.00 % )" { } { } 0} } { { "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" "" "" { Report "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" Compiler "count_deng" "UNKNOWN" "V1" "D:/第三周 试验 07607邓习海/db/count_deng.quartus_db" { Floorplan "" "" "8.000 ns" { q[0] q[2] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns + Shortest register " "Info: + Shortest clock path from clock clk to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 4 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 4; CLK Node = 'clk'" { } { { "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" "" "" { Report "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" Compiler "count_deng" "UNKNOWN" "V1" "D:/第三周 试验 07607邓习海/db/count_deng.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/第三周 试验 07607邓习海/count_deng.vhd" "" "" { Text "D:/第三周 试验 07607邓习海/count_deng.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns q\[2\] 2 REG LC6 6 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC6; Fanout = 6; REG Node = 'q\[2\]'" { } { { "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" "" "" { Report "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" Compiler "count_deng" "UNKNOWN" "V1" "D:/第三周 试验 07607邓习海/db/count_deng.quartus_db" { Floorplan "" "" "0.000 ns" { clk q[2] } "NODE_NAME" } } } { "D:/第三周 试验 07607邓习海/count_deng.vhd" "" "" { Text "D:/第三周 试验 07607邓习海/count_deng.vhd" 21 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" { } { } 0} } { { "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" "" "" { Report "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" Compiler "count_deng" "UNKNOWN" "V1" "D:/第三周 试验 07607邓习海/db/count_deng.quartus_db" { Floorplan "" "" "3.000 ns" { clk q[2] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns - Longest register " "Info: - Longest clock path from clock clk to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 4 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 4; CLK Node = 'clk'" { } { { "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" "" "" { Report "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" Compiler "count_deng" "UNKNOWN" "V1" "D:/第三周 试验 07607邓习海/db/count_deng.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/第三周 试验 07607邓习海/count_deng.vhd" "" "" { Text "D:/第三周 试验 07607邓习海/count_deng.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns q\[0\] 2 REG LC3 5 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC3; Fanout = 5; REG Node = 'q\[0\]'" { } { { "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" "" "" { Report "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" Compiler "count_deng" "UNKNOWN" "V1" "D:/第三周 试验 07607邓习海/db/count_deng.quartus_db" { Floorplan "" "" "0.000 ns" { clk q[0] } "NODE_NAME" } } } { "D:/第三周 试验 07607邓习海/count_deng.vhd" "" "" { Text "D:/第三周 试验 07607邓习海/count_deng.vhd" 21 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" { } { } 0} } { { "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" "" "" { Report "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" Compiler "count_deng" "UNKNOWN" "V1" "D:/第三周 试验 07607邓习海/db/count_deng.quartus_db" { Floorplan "" "" "3.000 ns" { clk q[0] } "NODE_NAME" } } } } 0} } { { "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" "" "" { Report "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" Compiler "count_deng" "UNKNOWN" "V1" "D:/第三周 试验 07607邓习海/db/count_deng.quartus_db" { Floorplan "" "" "3.000 ns" { clk q[2] } "NODE_NAME" } } } { "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" "" "" { Report "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" Compiler "count_deng" "UNKNOWN" "V1" "D:/第三周 试验 07607邓习海/db/count_deng.quartus_db" { Floorplan "" "" "3.000 ns" { clk q[0] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" { } { { "D:/第三周 试验 07607邓习海/count_deng.vhd" "" "" { Text "D:/第三周 试验 07607邓习海/count_deng.vhd" 21 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" { } { { "D:/第三周 试验 07607邓习海/count_deng.vhd" "" "" { Text "D:/第三周 试验 07607邓习海/count_deng.vhd" 21 -1 0 } } } 0} } { { "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" "" "" { Report "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" Compiler "count_deng" "UNKNOWN" "V1" "D:/第三周 试验 07607邓习海/db/count_deng.quartus_db" { Floorplan "" "" "8.000 ns" { q[0] q[2] } "NODE_NAME" } } } { "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" "" "" { Report "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" Compiler "count_deng" "UNKNOWN" "V1" "D:/第三周 试验 07607邓习海/db/count_deng.quartus_db" { Floorplan "" "" "3.000 ns" { clk q[2] } "NODE_NAME" } } } { "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" "" "" { Report "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" Compiler "count_deng" "UNKNOWN" "V1" "D:/第三周 试验 07607邓习海/db/count_deng.quartus_db" { Floorplan "" "" "3.000 ns" { clk q[0] } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk y\[3\] q\[3\] 8.000 ns register " "Info: tco from clock clk to destination pin y\[3\] through register q\[3\] is 8.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns + Longest register " "Info: + Longest clock path from clock clk to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 4 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 4; CLK Node = 'clk'" { } { { "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" "" "" { Report "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" Compiler "count_deng" "UNKNOWN" "V1" "D:/第三周 试验 07607邓习海/db/count_deng.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/第三周 试验 07607邓习海/count_deng.vhd" "" "" { Text "D:/第三周 试验 07607邓习海/count_deng.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns q\[3\] 2 REG LC8 4 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC8; Fanout = 4; REG Node = 'q\[3\]'" { } { { "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" "" "" { Report "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" Compiler "count_deng" "UNKNOWN" "V1" "D:/第三周 试验 07607邓习海/db/count_deng.quartus_db" { Floorplan "" "" "0.000 ns" { clk q[3] } "NODE_NAME" } } } { "D:/第三周 试验 07607邓习海/count_deng.vhd" "" "" { Text "D:/第三周 试验 07607邓习海/count_deng.vhd" 21 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" { } { } 0} } { { "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" "" "" { Report "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" Compiler "count_deng" "UNKNOWN" "V1" "D:/第三周 试验 07607邓习海/db/count_deng.quartus_db" { Floorplan "" "" "3.000 ns" { clk q[3] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" { } { { "D:/第三周 试验 07607邓习海/count_deng.vhd" "" "" { Text "D:/第三周 试验 07607邓习海/count_deng.vhd" 21 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.000 ns + Longest register pin " "Info: + Longest register to pin delay is 4.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q\[3\] 1 REG LC8 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8; Fanout = 4; REG Node = 'q\[3\]'" { } { { "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" "" "" { Report "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" Compiler "count_deng" "UNKNOWN" "V1" "D:/第三周 试验 07607邓习海/db/count_deng.quartus_db" { Floorplan "" "" "" { q[3] } "NODE_NAME" } } } { "D:/第三周 试验 07607邓习海/count_deng.vhd" "" "" { Text "D:/第三周 试验 07607邓习海/count_deng.vhd" 21 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 4.000 ns y\[3\] 2 PIN PIN_9 0 " "Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_9; Fanout = 0; PIN Node = 'y\[3\]'" { } { { "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" "" "" { Report "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" Compiler "count_deng" "UNKNOWN" "V1" "D:/第三周 试验 07607邓习海/db/count_deng.quartus_db" { Floorplan "" "" "4.000 ns" { q[3] y[3] } "NODE_NAME" } } } { "D:/第三周 试验 07607邓习海/count_deng.vhd" "" "" { Text "D:/第三周 试验 07607邓习海/count_deng.vhd" 11 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns 100.00 % " "Info: Total cell delay = 4.000 ns ( 100.00 % )" { } { } 0} } { { "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" "" "" { Report "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" Compiler "count_deng" "UNKNOWN" "V1" "D:/第三周 试验 07607邓习海/db/count_deng.quartus_db" { Floorplan "" "" "4.000 ns" { q[3] y[3] } "NODE_NAME" } } } } 0} } { { "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" "" "" { Report "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" Compiler "count_deng" "UNKNOWN" "V1" "D:/第三周 试验 07607邓习海/db/count_deng.quartus_db" { Floorplan "" "" "3.000 ns" { clk q[3] } "NODE_NAME" } } } { "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" "" "" { Report "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" Compiler "count_deng" "UNKNOWN" "V1" "D:/第三周 试验 07607邓习海/db/count_deng.quartus_db" { Floorplan "" "" "4.000 ns" { q[3] y[3] } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk y\[0\] q\[0\] 8.000 ns register " "Info: Minimum tco from clock clk to destination pin y\[0\] through register q\[0\] is 8.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns + Shortest register " "Info: + Shortest clock path from clock clk to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 4 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 4; CLK Node = 'clk'" { } { { "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" "" "" { Report "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" Compiler "count_deng" "UNKNOWN" "V1" "D:/第三周 试验 07607邓习海/db/count_deng.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/第三周 试验 07607邓习海/count_deng.vhd" "" "" { Text "D:/第三周 试验 07607邓习海/count_deng.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns q\[0\] 2 REG LC3 5 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC3; Fanout = 5; REG Node = 'q\[0\]'" { } { { "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" "" "" { Report "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" Compiler "count_deng" "UNKNOWN" "V1" "D:/第三周 试验 07607邓习海/db/count_deng.quartus_db" { Floorplan "" "" "0.000 ns" { clk q[0] } "NODE_NAME" } } } { "D:/第三周 试验 07607邓习海/count_deng.vhd" "" "" { Text "D:/第三周 试验 07607邓习海/count_deng.vhd" 21 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" { } { } 0} } { { "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" "" "" { Report "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" Compiler "count_deng" "UNKNOWN" "V1" "D:/第三周 试验 07607邓习海/db/count_deng.quartus_db" { Floorplan "" "" "3.000 ns" { clk q[0] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" { } { { "D:/第三周 试验 07607邓习海/count_deng.vhd" "" "" { Text "D:/第三周 试验 07607邓习海/count_deng.vhd" 21 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.000 ns + Shortest register pin " "Info: + Shortest register to pin delay is 4.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q\[0\] 1 REG LC3 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3; Fanout = 5; REG Node = 'q\[0\]'" { } { { "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" "" "" { Report "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" Compiler "count_deng" "UNKNOWN" "V1" "D:/第三周 试验 07607邓习海/db/count_deng.quartus_db" { Floorplan "" "" "" { q[0] } "NODE_NAME" } } } { "D:/第三周 试验 07607邓习海/count_deng.vhd" "" "" { Text "D:/第三周 试验 07607邓习海/count_deng.vhd" 21 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 4.000 ns y\[0\] 2 PIN PIN_12 0 " "Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_12; Fanout = 0; PIN Node = 'y\[0\]'" { } { { "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" "" "" { Report "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" Compiler "count_deng" "UNKNOWN" "V1" "D:/第三周 试验 07607邓习海/db/count_deng.quartus_db" { Floorplan "" "" "4.000 ns" { q[0] y[0] } "NODE_NAME" } } } { "D:/第三周 试验 07607邓习海/count_deng.vhd" "" "" { Text "D:/第三周 试验 07607邓习海/count_deng.vhd" 11 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns 100.00 % " "Info: Total cell delay = 4.000 ns ( 100.00 % )" { } { } 0} } { { "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" "" "" { Report "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" Compiler "count_deng" "UNKNOWN" "V1" "D:/第三周 试验 07607邓习海/db/count_deng.quartus_db" { Floorplan "" "" "4.000 ns" { q[0] y[0] } "NODE_NAME" } } } } 0} } { { "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" "" "" { Report "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" Compiler "count_deng" "UNKNOWN" "V1" "D:/第三周 试验 07607邓习海/db/count_deng.quartus_db" { Floorplan "" "" "3.000 ns" { clk q[0] } "NODE_NAME" } } } { "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" "" "" { Report "D:/第三周 试验 07607邓习海/db/count_deng_cmp.qrpt" Compiler "count_deng" "UNKNOWN" "V1" "D:/第三周 试验 07607邓习海/db/count_deng.quartus_db" { Floorplan "" "" "4.000 ns" { q[0] y[0] } "NODE_NAME" } } } } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1 " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat May 23 08:57:10 2009 " "Info: Processing ended: Sat May 23 08:57:10 2009" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0} } { } 0}
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