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用VHDL语言实现8421码的十进制计数器

--vhdl code for count10
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity count10 is
	port(
	clk,clear:in std_logic;
	q:out std_logic_vector(3 downto 0));
end count10;

architecture a of count10 is
	signal q_temp:std_logic_vector(3 downto 0);
begin
	process(clk)
	begin
	if(clk'event and clk='1') then
		if clear='0' then
		q_temp<="0000";
		elsif q_temp="1001" then
		q_temp<="0000";
		else
		q_temp<=q_temp+1;
		end if;
	end if;
	end process;
	q<=q_temp;
end a;