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</style></HEAD><BODY align=left style='background-color: #ffffff;'><DIV align=left><TABLE width=95% border=0 cellpadding=2><TR><TD><TABLE cellpadding=2 border=0 ><TR><WIZARD></WIZARD><TD><H1>Generation Report - 8B10B Encoder/Decoder v1.4.0</H1></TD></TR></TABLE></TD></TR><TR><TD><TABLE cellpadding=2 border=1 width=60%><TR><TD><B>Entity Name</B></TD><TD>ENC_aot1151_enc8b10b</TD></TR><TR><TD><B>Variation Name</B></TD><TD>ENC</TD></TR><TR><TD><B>Variation HDL</B></TD><TD>Verilog HDL</TD></TR><TR><TD><B>Output Directory</B></TD><TD>E:\examples\Example-8-2\IP_ENC</TD></TR></TABLE></TD></TR><TR><TD><h2>File Summary</h2>IP Toolbench is creating the following files in the output directory:</TD></TR><TR><TD><TABLE cellspacing=2 cellpadding=2 border=1 width=100%><TR align=left><TH align=left align=top width=25%><B>File</B></TH><TH align=left><B>Description</B></TH></TR><TR><TD>ENC.v</TD><TD>A MegaCore<small><sup>®</sup></small> function variation file, which defines a Verilog HDL top-level description of the custom MegaCore function. Instantiate the entity defined by this file inside of your design. Include this file when compiling your design in the Quartus II software.</TD></TR><TR><TD>ENC_inst.v</TD><TD>Verilog HDL sample instantiation file</TD></TR><TR><TD>ENC.cmp</TD><TD>A VHDL component declaration for the MegaCore function variation. Add the contents of this file to any VHDL architecture that instantiates the MegaCore function.</TD></TR><TR><TD>ENC.inc</TD><TD>An AHDL include declaration file for the MegaCore function variation. Include this file with any AHDL architecture that instantiates the MegaCore function.</TD></TR><TR><TD>ENC_bb.v</TD><TD>Verilog HDL black-box file for the MegaCore function variation. Use this file when using a third-party EDA tool to synthesize your design.</TD></TR><TR><TD>ENC.bsf</TD><TD>Quartus<small><sup>®</sup></small> II symbol file for the MegaCore function variation. You can use this file in the Quartus II block diagram editor.</TD></TR><TR><TD>ENC_tb.v</TD><TD>Testbench file.</TD></TR><TR><TD>ENC_simfiles.vnc</TD><TD>Verilog include file list for testbench.</TD></TR><TR><TD>ENC_run_modelsim_verilog</TD><TD>Script to run testbench.</TD></TR><TR><TD>ENC_run_modelsim_vhdl</TD><TD>Script to run testbench.</TD></TR><TR><TD>ENC_aot1151_ed8b10b.ocp</TD><TD>OpenCore Plus file.</TD></TR><TR><TD>ENC_aot1151_ed8b10b.tcl</TD><TD>Tcl script.</TD></TR><TR><TD>ENC_aot1151_enc8b10b.v</TD><TD>Encrypted Verilog HDL RTL for core.</TD></TR><TR><TD>ENC.vo</TD><TD>Verilog HDL IP functional simulation model.</TD></TR><TR><TD>ENC.html</TD><TD>The MegaCore function report file.</TD></TR></TABLE></TD></TR><TR><TD><h2>MegaCore Function Variation File Ports</h2><TABLE border=1 cellpadding=2 cellspacing=0 width=75%><TR align=left><TH align=left><B>Name</B></TH><TH align=left><B>Direction</B></TH><TH align=left><B>Width</B></TH></TR><TR><TD>clk</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>reset_n</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>idle_ins</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>kin</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>ena</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>datain</TD><TD>INPUT</TD><TD>8</TD></TR><TR><TD>kerr</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>dataout</TD><TD>OUTPUT</TD><TD>10</TD></TR><TR><TD>valid</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>rdin</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>rdforce</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>rdout</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>rdcascade</TD><TD>OUTPUT</TD><TD>1</TD></TR></TABLE></TD></TR></TD></TR></TABLE></DIV></BODY></HTML>⌨️ 快捷键说明
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