cnt4.vhd

来自「这是用VHDL设计的十进制计数器」· VHDL 代码 · 共 15 行

ENTITY CNT4 IS     
  PORT ( CLK : IN BIT ; 
           Q  : BUFFER INTEGER RANGE 15 DOWNTO 0 ) ; 
  END ; 
ARCHITECTURE bhv OF CNT4 IS
  BEGIN 
  PROCESS (CLK)     
    BEGIN         
      IF  CLK'EVENT AND CLK = '1'  THEN 
        Q <= Q + 1 ;    
      END IF;
  END PROCESS ;
END bhv;