cnt42.vhd

来自「这是用VHDL设计的十进制计数器」· VHDL 代码 · 共 20 行

LIBRARY IEEE ; 
 USE IEEE.STD_LOGIC_1164.ALL ; 
 USE IEEE.STD_LOGIC_UNSIGNED.ALL ; 
 ENTITY CNT42 IS     
 PORT ( CLK : IN STD_LOGIC ; 
           Q  : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)  ) ; 
 END CNT42; 
 ARCHITECTURE bhv OF CNT42 IS
SIGNAL Q1 : STD_LOGIC_VECTOR(3 DOWNTO 0);
 BEGIN 
   PROCESS (CLK)     
   BEGIN         
       IF  CLK'EVENT AND CLK = '1'  THEN 
            Q1 <= Q1 + 1 ;    
       END IF;
             Q <= Q1 ;    
   END PROCESS ;
 END bhv;