fft_2048.v

rtl实现的fft变换

module fft_2048(
  rst,
  clk,
  inv_i,
  data_imag_in,
  data_real_in,
  master_sink_dav,
  master_sink_ena,
  master_sink_sop,
  fft_imag_out,
  fft_real_out,
  exponent_out,
  master_source_dav,
  master_source_ena,
  master_source_sop,
  master_source_eop
);


input  rst;
input  clk;
input  inv_i;
input  [9:0] data_imag_in;
input  [9:0] data_real_in;
input  master_sink_dav;
output  master_sink_ena;
input   master_sink_sop;
output  [9:0] fft_imag_out;
output  [9:0] fft_real_out;
output  [5:0] exponent_out;
input  master_source_dav;
output  master_source_ena;
output  master_source_sop;
output  master_source_eop;

wire  master_sink_ena;
wire  master_sink_sop;
wire  master_source_ena;
wire  master_source_sop;
wire  master_source_eop;
wire  [9:0] fft_imag_out;
wire  [9:0] fft_real_out;
wire  [5:0] exponent_out;

//-------------------------------------------
wire [11:0] real_sw_out, image_sw_out;
wire [11:0] xr,xi,yr,yi;
reg [11:0] wdata2_real_up, wdata2_image_up;
reg [11:0] wdata2_real_dn, wdata2_image_dn;

wire [11:0] real_output, image_output;

wire ram_up_wen, ram_dn_wen;
wire [9:0] ram_up_waddr, ram_dn_waddr;
wire [23:0] ram_up_wdata, ram_dn_wdata;

wire ram_up_ren, ram_dn_ren;
wire [9:0] ram_up_raddr, ram_dn_raddr;
wire [23:0] ram_up_rdata, ram_dn_rdata;

wire rom_ren;
wire [9:0] rom_raddr;
wire [9:0] rom_cos, rom_sin;

wire frame_out_enb,frame_out_sop,frame_out_eop;

wire ram_up_wsel, ram_up_rsel;
wire frame_input_on ;
wire ram_rdata_valid;
wire wr_stage_cmplt ;
wire bfly_finish    ;

wire shift_out_valid;
wire bfly_out_valid ;

wire [1:0] shift_ctrl;

fft_ctrl fft_ctrl_inst (
  .rst              ( rst              ),
  .clk              ( clk              ),
  .frame_in_dav     ( master_sink_dav  ),
  .frame_in_enb     ( master_sink_ena  ),
  .frame_in_sop     ( master_sink_sop  ),
  .frame_out_dav    ( master_source_dav),
  .frame_out_enb    ( frame_out_enb    ),
  .frame_out_sop    ( frame_out_sop    ),
  .frame_out_eop    ( frame_out_eop    ),
  .ram_up_wen       ( ram_up_wen       ),
  .ram_up_ren       ( ram_up_ren       ),
  .ram_up_waddr     ( ram_up_waddr     ),
  .ram_up_raddr     ( ram_up_raddr     ),
  .ram_dn_wen       ( ram_dn_wen       ),
  .ram_dn_ren       ( ram_dn_ren       ),
  .ram_dn_waddr     ( ram_dn_waddr     ),
  .ram_dn_raddr     ( ram_dn_raddr     ),
  .rom_ren          ( rom_ren          ),
  .rom_raddr        ( rom_raddr        ),
  .ram_up_wsel      ( ram_up_wsel      ), 
  .ram_up_rsel      ( ram_up_rsel      ), 
  .frame_input_on   ( frame_input_on   ), 
  .ram_rdata_valid  ( ram_rdata_valid  ),
  .wr_stage_cmplt   ( wr_stage_cmplt   ),
  .bfly_finish      ( bfly_finish      )
);


input_sw input_sw_inst (
  .inv_i         ( inv_i          ),
  .fft_real_in   ( data_real_in    ),
  .fft_image_in  ( data_imag_in   ),
  .fft_real_out  ( real_sw_out    ),
  .fft_image_out ( image_sw_out   )
);

ram1024x24_dp  ram1024x24_dp_up_inst (
	.clock     ( clk          ),
	.wren      ( ram_up_wen   ),
	.wraddress ( ram_up_waddr ),
	.data      ( ram_up_wdata ),
	.rden      ( ram_up_ren   ),
	.rdaddress ( ram_up_raddr ),
	.q         ( ram_up_rdata )
);

ram1024x24_dp  ram1024x24_dp_dn_inst (
	.clock     ( clk          ),
	.wren      ( ram_dn_wen   ),
	.wraddress ( ram_dn_waddr ),
	.data      ( ram_dn_wdata ),
	.rden      ( ram_dn_ren   ),
	.rdaddress ( ram_dn_raddr ),
	.q         ( ram_dn_rdata )
);

wire [8:0] rom_raddr_2;
wire [9:0] rom_cos_2,rom_sin_2;
reg [1:0] d2t_reg;

always @(posedge rst or posedge clk) begin
	if(rst)
		d2t_reg <= 2'b00;
	else
		d2t_reg <= {d2t_reg[0],rom_raddr[9]};
end

assign rom_raddr_2 = rom_raddr[9] ? ~rom_raddr[8:0] : rom_raddr[8:0];

assign rom_cos = d2t_reg[1] ? (~rom_cos_2 + 10'h1) : rom_cos_2;
assign rom_sin = rom_sin_2 ;

rom512x10_cos_sp	rom512x10_cos_sp_inst (
	.clock   ( clk       ),
	.clken   ( rom_ren   ),
	.address ( rom_raddr_2 ),
	.q       ( rom_cos_2   )
);

rom512x10_sin_sp	rom512x10_sin_sp_inst (
	.clock   ( clk       ),
	.clken   ( rom_ren   ),
	.address ( rom_raddr_2 ),
	.q       ( rom_sin_2   )
);

wire [9:0] up_out_real, up_out_image;
wire [9:0] dn_out_real, dn_out_image;

shift_process shift_process_inst (
  .rst              ( rst                 )  ,
  .clk              ( clk                 )  ,
  .shift_in_valid   ( ram_rdata_valid     )  ,
  .shift_out_valid  ( shift_out_valid     )  ,
  .shift_ctrl       ( shift_ctrl          )  ,
  .up_in_real       ( ram_up_rdata[23:12] )  ,
  .up_in_image      ( ram_up_rdata[11:0]   )  ,
  .dn_in_real       ( ram_dn_rdata[23:12] )  ,
  .dn_in_image      ( ram_dn_rdata[11:0]   )  ,
  .up_out_real      ( up_out_real         )  ,
  .up_out_image     ( up_out_image        )  ,
  .dn_out_real      ( dn_out_real         )  ,
  .dn_out_image     ( dn_out_image        )   
);

bfly_r2dit bfly_r2dit_inst (
  .rst       ( rst             ),
  .clk       ( clk             ),
  .din_av    ( shift_out_valid ),
  .out_enb   ( bfly_out_valid  ),
  .ar        ( up_out_real     ),
  .ai        ( up_out_image    ),
  .br        ( dn_out_real     ),
  .bi        ( dn_out_image    ),
  .wc        ( rom_cos         ),
  .ws        ( rom_sin         ),
  .xr        ( xr              ),
  .xi        ( xi              ),
  .yr        ( yr              ),
  .yi        ( yi              ) 
);

always @(posedge rst or posedge clk) begin
  if(rst) begin
	wdata2_real_up  <= 12'h0;
	wdata2_image_up <= 12'h0;
  end
  else if(bfly_out_valid && ram_up_wsel) begin
	wdata2_real_up  <= yr;
	wdata2_image_up <= yi;
  end
end

always @(posedge rst or posedge clk) begin
  if(rst) begin
	wdata2_real_dn  <= 12'h0;
	wdata2_image_dn <= 12'h0;
  end
  else if(bfly_out_valid && !ram_up_wsel) begin
	wdata2_real_dn  <= yr;
	wdata2_image_dn <= yi;
  end
end

assign ram_up_wdata = (frame_input_on) ? {real_sw_out,image_sw_out} : 
	                                 (ram_up_wsel) ? {xr,xi} : {wdata2_real_up,wdata2_image_up};
assign ram_dn_wdata = (frame_input_on) ? {real_sw_out,image_sw_out} : 
	                                 (ram_up_wsel) ? {wdata2_real_dn,wdata2_image_dn} : {xr,xi};

overflow_detect overflow_detect_inst (
  .rst               ( rst            )  ,
  .clk               ( clk            )  ,
  .bfly_out_valid    ( bfly_out_valid )  ,
  .wr_stage_cmplt    ( wr_stage_cmplt )  ,
  .xr_h3             ( xr[11:9]        )  ,
  .xi_h3             ( xi[11:9]        )  ,
  .yr_h3             ( yr[11:9]        )  ,
  .yi_h3             ( yi[11:9]        )  ,
  .shift_ctrl_clr    ( frame_out_eop  )  ,
  .shift_ctrl        ( shift_ctrl     )  
);

// output
assign real_output =  (frame_out_enb && ram_up_rsel) ? ram_up_rdata[23:12] :
	                                               ram_dn_rdata[23:12];
assign image_output = (frame_out_enb && ram_up_rsel) ? ram_up_rdata[11:0] :
	                                               ram_dn_rdata[11:0];

output_sw output_sw_inst (
  .rst               ( rst               ),
  .clk               ( clk               ),
  .inv_i             ( inv_i             ),
  .exp_clr           ( master_sink_sop   ),
  .wr_stage_cmplt    ( wr_stage_cmplt    ),
  .frame_out_enb     ( frame_out_enb     ),
  .frame_out_sop     ( frame_out_sop     ),
  .frame_out_eop     ( frame_out_eop     ),
  .shift_ctrl        ( shift_ctrl        ),
  .fft_real_in       ( real_output       ),
  .fft_image_in      ( image_output      ),
  .fft_real_out      ( fft_real_out      ),
  .fft_image_out     ( fft_imag_out      ),
  .exponent_out      ( exponent_out      ),
  .master_source_enb ( master_source_ena ),
  .master_source_sop ( master_source_sop ),
  .master_source_eop ( master_source_eop )
);

endmodule