input_sw.v

来自「rtl实现的fft变换」· Verilog 代码 · 共 22 行

module input_sw (
  inv_i,
  fft_real_in,
  fft_image_in,
  fft_real_out,
  fft_image_out
);

input inv_i;
input [9:0] fft_real_in, fft_image_in;
output [11:0] fft_real_out, fft_image_out;

wire [9:0] image_inv;

assign fft_real_out = {fft_real_in[9],fft_real_in[9],fft_real_in};

assign image_inv = (fft_image_in==10'b10_0000_0000) ? 10'b01_1111_1111 : (~fft_image_in + 1'b1);
assign fft_image_out = (inv_i) ? {   image_inv[9],   image_inv[9],   image_inv} : 
	                         {fft_image_in[9],fft_image_in[9],fft_image_in};

endmodule