overflow_detect.v

来自「rtl实现的fft变换」· Verilog 代码 · 共 63 行

module overflow_detect (
  rst,
  clk,
  bfly_out_valid,
  wr_stage_cmplt,
  xr_h3,
  xi_h3,
  yr_h3,
  yi_h3,
  shift_ctrl_clr,
  shift_ctrl
);

input rst,clk;
input bfly_out_valid;
input wr_stage_cmplt;
input [2:0] xr_h3,xi_h3,yr_h3,yi_h3;
input shift_ctrl_clr;
output [1:0] shift_ctrl;

reg [1:0] shift_ctrl;

wire [1:0] of_det;
reg  [1:0] of_flg;

assign of_det[1] = (xr_h3[2]^xr_h3[1]) | 
	           (xi_h3[2]^xi_h3[1]) | 
		   (yr_h3[2]^yr_h3[1]) |  
		   (yi_h3[2]^yi_h3[1]); 
assign of_det[0] = (xr_h3[1]^xr_h3[0]) | 
	           (xi_h3[1]^xi_h3[0]) | 
		   (yr_h3[1]^yr_h3[0]) |  
		   (yi_h3[1]^yi_h3[0]); 

always @(posedge rst or posedge clk) begin
  if(rst)
	  of_flg[1] <= 1'b0;
  else if(wr_stage_cmplt)
	  of_flg[1] <= 1'b0;
  else if(of_det[1] && !of_flg[1] && bfly_out_valid)
	  of_flg[1] <= 1'b1;
end

always @(posedge rst or posedge clk) begin
  if(rst)
	  of_flg[0] <= 1'b0;
  else if(wr_stage_cmplt)
	  of_flg[0] <= 1'b0;
  else if(of_det[0] && !of_flg[0] && bfly_out_valid)
	  of_flg[0] <= 1'b1;
end

always @(posedge rst or posedge clk) begin
  if(rst)
	  shift_ctrl <= 2'b00;
  else if(shift_ctrl_clr)
	  shift_ctrl <= 2'b00;
  else if(wr_stage_cmplt)
	  shift_ctrl <= of_flg[1] ? 2'b10 : of_flg;
end

endmodule