shift_process.v

rtl实现的fft变换

module shift_process (
  rst,
  clk,
  shift_in_valid,
  shift_out_valid,
  shift_ctrl,
  up_in_real,
  up_in_image,
  dn_in_real,
  dn_in_image,
  up_out_real,
  up_out_image,
  dn_out_real,
  dn_out_image
);

input rst, clk;
input shift_in_valid;
output shift_out_valid;
input [1:0] shift_ctrl;
input [11:0] up_in_real, up_in_image, dn_in_real, dn_in_image;
output [9:0] up_out_real, up_out_image, dn_out_real, dn_out_image;

reg shift_out_valid;
reg [9:0] up_out_real, up_out_image, dn_out_real, dn_out_image;

always @(posedge rst or posedge clk) begin
  if(rst) begin
    up_out_real  <= 10'h0;
    up_out_image <= 10'h0;
    dn_out_real  <= 10'h0;
    dn_out_image <= 10'h0;
  end
  else if(shift_in_valid) begin
    case(shift_ctrl)
      2'b00: begin  
             up_out_real  <=  up_in_real[9:0] ;
             up_out_image <= up_in_image[9:0] ;
             dn_out_real  <=  dn_in_real[9:0] ;
             dn_out_image <= dn_in_image[9:0] ;
      end
      2'b01: begin 
             up_out_real  <=  up_in_real[11] ? ( up_in_real[10:1]) : ( up_in_real[10:1] + {9'b0_0000_0000,  up_in_real[0]}) ;
             up_out_image <= up_in_image[11] ? (up_in_image[10:1]) : (up_in_image[10:1] + {9'b0_0000_0000, up_in_image[0]}) ;
             dn_out_real  <=  dn_in_real[11] ? ( dn_in_real[10:1]) : ( dn_in_real[10:1] + {9'b0_0000_0000,  dn_in_real[0]}) ;
             dn_out_image <= dn_in_image[11] ? (dn_in_image[10:1]) : (dn_in_image[10:1] + {9'b0_0000_0000, dn_in_image[0]}) ;
      end
      2'b10: begin
             up_out_real  <=  ( up_in_real[11:2] )    ;
             up_out_image <=  (up_in_image[11:2] )    ;
             dn_out_real  <=  ( dn_in_real[11:2] )    ;
             dn_out_image <=  (dn_in_image[11:2] )    ;
      end
      default: begin
             up_out_real  <= 10'h0;
             up_out_image <= 10'h0;
             dn_out_real  <= 10'h0;
             dn_out_image <= 10'h0;
      end
    endcase
  end
end

always @(posedge rst or posedge clk) begin
  if(rst) 
	  shift_out_valid <= 1'b0;
  else
	  shift_out_valid <= shift_in_valid;
end

endmodule