bfly_r2dit.v

rtl实现的fft变换

module bfly_r2dit (
  rst,
  clk,
  din_av,
  out_enb,
  ar,
  ai,
  br,
  bi,
  wc,
  ws,
  xr,
  xi,
  yr,
  yi
);

input rst, clk;
input din_av;
output out_enb;
input [9:0] ar,ai,br,bi;
input [9:0] wc,ws;
output [11:0] xr,xi,yr,yi;

//----------------------------------------------------
reg [11:0] xr, xi, yr, yi;
reg out_enb;

//----------------------------------------------------
// B * W
wire [19:0] real_cos, real_sin, image_cos, image_sin;
reg [19:0] real_cos_reg, real_sin_reg, image_cos_reg, image_sin_reg;
reg [9:0] ar_d1t, ai_d1t;


mult10x10 mult10x10_real_cos (
	.dataa      ( br       ),
	.datab      ( wc       ),
	.result     ( real_cos )
);

mult10x10 mult10x10_real_sin (
	.dataa      ( br       ),
	.datab      ( ws       ),
	.result     ( real_sin )
);

mult10x10 mult10x10_image_cos (
	.dataa      ( bi        ),
	.datab      ( wc        ),
	.result     ( image_cos )
);

mult10x10 mult10x10_image_sin (
	.dataa      ( bi        ),
	.datab      ( ws        ),
	.result     ( image_sin )
);

always @(posedge rst or posedge clk) begin
  if(rst) begin
    real_cos_reg   <= 20'h0;
    real_sin_reg   <= 20'h0;
    image_cos_reg  <= 20'h0;
    image_sin_reg  <= 20'h0;
    ar_d1t <= 10'h0;
    ai_d1t <= 10'h0;
  end
  else if (din_av) begin  
    real_cos_reg   <=  real_cos[19:0] ;
    real_sin_reg   <=  real_sin[19:0] ;
    image_cos_reg  <= image_cos[19:0] ;
    image_sin_reg  <= image_sin[19:0] ;
    ar_d1t <= ar;
    ai_d1t <= ai;
  end
end



//assign cr = real_cos_reg + image_sin_reg;
//assign ci = image_cos_reg - real_sin_reg;
// 2bit sign extended
wire [19:0] cr, ci;
assign cr =  real_cos_reg - image_sin_reg;
assign ci = image_cos_reg +  real_sin_reg;

wire [20:0] xr_c,xi_c,yr_c,yi_c;
assign xr_c = {ar_d1t[9],ar_d1t[9],ar_d1t,9'b0_0000_0000} + {cr[19],cr}  ;
assign xi_c = {ai_d1t[9],ai_d1t[9],ai_d1t,9'b0_0000_0000} + {ci[19],ci}  ;
assign yr_c = {ar_d1t[9],ar_d1t[9],ar_d1t,9'b0_0000_0000} - {cr[19],cr}  ;
assign yi_c = {ai_d1t[9],ai_d1t[9],ai_d1t,9'b0_0000_0000} - {ci[19],ci}  ;

//----------------------------------------------------
// X = A + B*W
// Y = A - B*W
reg din_dav_d1t;

always @(posedge rst or posedge clk) begin
  if(rst) begin
    xr <= 12'h0;
    xi <= 12'h0;
    yr <= 12'h0;
    yi <= 12'h0;
  end
  else if(din_dav_d1t) begin
    xr <= (xr_c[20]) ? (xr_c[20:9] + {11'b000_0000_0000, xr_c[8] & (|xr_c[7:0]) }) : (xr_c[20:9] + {11'b000_0000_0000,xr_c[8]});
    xi <= (xi_c[20]) ? (xi_c[20:9] + {11'b000_0000_0000, xi_c[8] & (|xi_c[7:0]) }) : (xi_c[20:9] + {11'b000_0000_0000,xi_c[8]});
    yr <= (yr_c[20]) ? (yr_c[20:9] + {11'b000_0000_0000, yr_c[8] & (|yr_c[7:0]) }) : (yr_c[20:9] + {11'b000_0000_0000,yr_c[8]});
    yi <= (yi_c[20]) ? (yi_c[20:9] + {11'b000_0000_0000, yi_c[8] & (|yi_c[7:0]) }) : (yi_c[20:9] + {11'b000_0000_0000,yi_c[8]});
  end
end

always @(posedge rst or posedge clk) begin
  if(rst) begin
    din_dav_d1t <= 1'b0;
    out_enb     <= 1'b0;
  end
  else begin
    din_dav_d1t <= din_av;
    out_enb     <= din_dav_d1t;
  end
end

endmodule