plj.map.qmsg

基于CPLD的数字频率计

{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "DATAIN xiANshi.vhd(74) " "Warning (10492): VHDL Process Statement warning at xiANshi.vhd(74): signal \"DATAIN\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "xiANshi.vhd" "" { Text "F:/数字频率计1/xiANshi.vhd" 74 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "DATAIN xiANshi.vhd(76) " "Warning (10492): VHDL Process Statement warning at xiANshi.vhd(76): signal \"DATAIN\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "xiANshi.vhd" "" { Text "F:/数字频率计1/xiANshi.vhd" 76 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "DATAIN xiANshi.vhd(78) " "Warning (10492): VHDL Process Statement warning at xiANshi.vhd(78): signal \"DATAIN\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "xiANshi.vhd" "" { Text "F:/数字频率计1/xiANshi.vhd" 78 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "DATAIN xiANshi.vhd(80) " "Warning (10492): VHDL Process Statement warning at xiANshi.vhd(80): signal \"DATAIN\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "xiANshi.vhd" "" { Text "F:/数字频率计1/xiANshi.vhd" 80 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "DATAIN xiANshi.vhd(82) " "Warning (10492): VHDL Process Statement warning at xiANshi.vhd(82): signal \"DATAIN\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "xiANshi.vhd" "" { Text "F:/数字频率计1/xiANshi.vhd" 82 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "DATAIN xiANshi.vhd(84) " "Warning (10492): VHDL Process Statement warning at xiANshi.vhd(84): signal \"DATAIN\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "xiANshi.vhd" "" { Text "F:/数字频率计1/xiANshi.vhd" 84 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "xiANshi.vhd(126) " "Info (10425): VHDL Case Statement information at xiANshi.vhd(126): OTHERS choice is never selected" {  } { { "xiANshi.vhd" "" { Text "F:/数字频率计1/xiANshi.vhd" 126 0 0 } }  } 0 10425 "VHDL Case Statement information at %1!s!: OTHERS choice is never selected" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "REG32B REG32B:inst2 " "Info: Elaborating entity \"REG32B\" for hierarchy \"REG32B:inst2\"" {  } { { "F.bdf" "inst2" { Schematic "F:/数字频率计1/F.bdf" { { -336 408 576 -240 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "TESTCTL TESTCTL:inst17 " "Info: Elaborating entity \"TESTCTL\" for hierarchy \"TESTCTL:inst17\"" {  } { { "F.bdf" "inst17" { Schematic "F:/数字频率计1/F.bdf" { { -480 408 544 -384 "inst17" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CLK2 TESTCTL.vhd(30) " "Warning (10492): VHDL Process Statement warning at TESTCTL.vhd(30): signal \"CLK2\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "TESTCTL.vhd" "" { Text "F:/数字频率计1/TESTCTL.vhd" 30 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CNT10 CNT10:inst10 " "Info: Elaborating entity \"CNT10\" for hierarchy \"CNT10:inst10\"" {  } { { "F.bdf" "inst10" { Schematic "F:/数字频率计1/F.bdf" { { -160 840 984 -64 "inst10" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "KZ KZ:inst1 " "Info: Elaborating entity \"KZ\" for hierarchy \"KZ:inst1\"" {  } { { "F.bdf" "inst1" { Schematic "F:/数字频率计1/F.bdf" { { -232 360 544 -8 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "SEG_DATA\[0\] VCC " "Warning: Pin \"SEG_DATA\[0\]\" stuck at VCC" {  } { { "F.bdf" "" { Schematic "F:/数字频率计1/F.bdf" { { 24 864 1041 40 "SEG_DATA\[7..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "xiANshi.vhd" "" { Text "F:/数字频率计1/xiANshi.vhd" 40 -1 0 } } { "xiANshi.vhd" "" { Text "F:/数字频率计1/xiANshi.vhd" 40 -1 0 } } { "xiANshi.vhd" "" { Text "F:/数字频率计1/xiANshi.vhd" 40 -1 0 } } { "xiANshi.vhd" "" { Text "F:/数字频率计1/xiANshi.vhd" 40 -1 0 } } { "xiANshi.vhd" "" { Text "F:/数字频率计1/xiANshi.vhd" 40 -1 0 } } { "xiANshi.vhd" "" { Text "F:/数字频率计1/xiANshi.vhd" 40 -1 0 } } { "xiANshi.vhd" "" { Text "F:/数字频率计1/xiANshi.vhd" 40 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "330 " "Info: Implemented 330 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "310 " "Info: Implemented 310 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 14 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 14 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Jan 10 14:37:12 2009 " "Info: Processing ended: Sat Jan 10 14:37:12 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}