plj.fit.qmsg

基于CPLD的数字频率计

{ "Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Info: Moving registers into LUTs to improve timing and density" {  } {  } 0 0 "Moving registers into LUTs to improve timing and density" 0 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Info: Started processing fast register assignments" {  } {  } 0 0 "Started processing fast register assignments" 0 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Info: Finished processing fast register assignments" {  } {  } 0 0 "Finished processing fast register assignments" 0 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "" "Info: Finished moving registers into LUTs" {  } {  } 0 0 "Finished moving registers into LUTs" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0 0 "Finished register packing" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Info: Fitter placement operations ending: elapsed time is 00:00:03" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "15.858 ns register pin " "Info: Estimated most critical path is register to pin delay of 15.858 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns XIANSHI:inst3\|en_xhdl3\[7\] 1 REG LAB_X10_Y9 19 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X10_Y9; Fanout = 19; REG Node = 'XIANSHI:inst3\|en_xhdl3\[7\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "plj" "UNKNOWN" "V1" "F:/数字频率计1/db/plj.quartus_db" { Floorplan "F:/数字频率计1/" "" "" { XIANSHI:inst3|en_xhdl3[7] } "NODE_NAME" } "" } } { "xiANshi.vhd" "" { Text "F:/数字频率计1/xiANshi.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.620 ns) + CELL(0.740 ns) 1.360 ns rtl~863 2 COMB LAB_X10_Y9 9 " "Info: 2: + IC(0.620 ns) + CELL(0.740 ns) = 1.360 ns; Loc. = LAB_X10_Y9; Fanout = 9; COMB Node = 'rtl~863'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "plj" "UNKNOWN" "V1" "F:/数字频率计1/db/plj.quartus_db" { Floorplan "F:/数字频率计1/" "" "1.360 ns" { XIANSHI:inst3|en_xhdl3[7] rtl~863 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.725 ns) + CELL(0.914 ns) 2.999 ns rtl~865 3 COMB LAB_X11_Y9 6 " "Info: 3: + IC(0.725 ns) + CELL(0.914 ns) = 2.999 ns; Loc. = LAB_X11_Y9; Fanout = 6; COMB Node = 'rtl~865'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "plj" "UNKNOWN" "V1" "F:/数字频率计1/db/plj.quartus_db" { Floorplan "F:/数字频率计1/" "" "1.639 ns" { rtl~863 rtl~865 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.690 ns) + CELL(0.740 ns) 5.429 ns XIANSHI:inst3\|seg_data_buf\[0\]~1864 4 COMB LAB_X11_Y8 1 " "Info: 4: + IC(1.690 ns) + CELL(0.740 ns) = 5.429 ns; Loc. = LAB_X11_Y8; Fanout = 1; COMB Node = 'XIANSHI:inst3\|seg_data_buf\[0\]~1864'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "plj" "UNKNOWN" "V1" "F:/数字频率计1/db/plj.quartus_db" { Floorplan "F:/数字频率计1/" "" "2.430 ns" { rtl~865 XIANSHI:inst3|seg_data_buf[0]~1864 } "NODE_NAME" } "" } } { "xiANshi.vhd" "" { Text "F:/数字频率计1/xiANshi.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.269 ns) + CELL(0.914 ns) 6.612 ns XIANSHI:inst3\|seg_data_buf\[0\]~1866 5 COMB LAB_X11_Y8 1 " "Info: 5: + IC(0.269 ns) + CELL(0.914 ns) = 6.612 ns; Loc. = LAB_X11_Y8; Fanout = 1; COMB Node = 'XIANSHI:inst3\|seg_data_buf\[0\]~1866'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "plj" "UNKNOWN" "V1" "F:/数字频率计1/db/plj.quartus_db" { Floorplan "F:/数字频率计1/" "" "1.183 ns" { XIANSHI:inst3|seg_data_buf[0]~1864 XIANSHI:inst3|seg_data_buf[0]~1866 } "NODE_NAME" } "" } } { "xiANshi.vhd" "" { Text "F:/数字频率计1/xiANshi.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.983 ns) + CELL(0.200 ns) 7.795 ns XIANSHI:inst3\|seg_data_buf\[0\]~1867 6 COMB LAB_X11_Y8 1 " "Info: 6: + IC(0.983 ns) + CELL(0.200 ns) = 7.795 ns; Loc. = LAB_X11_Y8; Fanout = 1; COMB Node = 'XIANSHI:inst3\|seg_data_buf\[0\]~1867'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "plj" "UNKNOWN" "V1" "F:/数字频率计1/db/plj.quartus_db" { Floorplan "F:/数字频率计1/" "" "1.183 ns" { XIANSHI:inst3|seg_data_buf[0]~1866 XIANSHI:inst3|seg_data_buf[0]~1867 } "NODE_NAME" } "" } } { "xiANshi.vhd" "" { Text "F:/数字频率计1/xiANshi.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.464 ns) + CELL(0.200 ns) 9.459 ns XIANSHI:inst3\|seg_data_buf\[0\]~1868 7 COMB LAB_X12_Y8 7 " "Info: 7: + IC(1.464 ns) + CELL(0.200 ns) = 9.459 ns; Loc. = LAB_X12_Y8; Fanout = 7; COMB Node = 'XIANSHI:inst3\|seg_data_buf\[0\]~1868'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "plj" "UNKNOWN" "V1" "F:/数字频率计1/db/plj.quartus_db" { Floorplan "F:/数字频率计1/" "" "1.664 ns" { XIANSHI:inst3|seg_data_buf[0]~1867 XIANSHI:inst3|seg_data_buf[0]~1868 } "NODE_NAME" } "" } } { "xiANshi.vhd" "" { Text "F:/数字频率计1/xiANshi.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.751 ns) + CELL(0.914 ns) 11.124 ns XIANSHI:inst3\|seg_data\[5\]~107 8 COMB LAB_X13_Y8 1 " "Info: 8: + IC(0.751 ns) + CELL(0.914 ns) = 11.124 ns; Loc. = LAB_X13_Y8; Fanout = 1; COMB Node = 'XIANSHI:inst3\|seg_data\[5\]~107'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "plj" "UNKNOWN" "V1" "F:/数字频率计1/db/plj.quartus_db" { Floorplan "F:/数字频率计1/" "" "1.665 ns" { XIANSHI:inst3|seg_data_buf[0]~1868 XIANSHI:inst3|seg_data[5]~107 } "NODE_NAME" } "" } } { "xiANshi.vhd" "" { Text "F:/数字频率计1/xiANshi.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.412 ns) + CELL(2.322 ns) 15.858 ns SEG_DATA\[5\] 9 PIN PIN_111 0 " "Info: 9: + IC(2.412 ns) + CELL(2.322 ns) = 15.858 ns; Loc. = PIN_111; Fanout = 0; PIN Node = 'SEG_DATA\[5\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "plj" "UNKNOWN" "V1" "F:/数字频率计1/db/plj.quartus_db" { Floorplan "F:/数字频率计1/" "" "4.734 ns" { XIANSHI:inst3|seg_data[5]~107 SEG_DATA[5] } "NODE_NAME" } "" } } { "F.bdf" "" { Schematic "F:/数字频率计1/F.bdf" { { 24 864 1041 40 "SEG_DATA\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.944 ns ( 43.79 % ) " "Info: Total cell delay = 6.944 ns ( 43.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.914 ns ( 56.21 % ) " "Info: Total interconnect delay = 8.914 ns ( 56.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "plj" "UNKNOWN" "V1" "F:/数字频率计1/db/plj.quartus_db" { Floorplan "F:/数字频率计1/" "" "15.858 ns" { XIANSHI:inst3|en_xhdl3[7] rtl~863 rtl~865 XIANSHI:inst3|seg_data_buf[0]~1864 XIANSHI:inst3|seg_data_buf[0]~1866 XIANSHI:inst3|seg_data_buf[0]~1867 XIANSHI:inst3|seg_data_buf[0]~1868 XIANSHI:inst3|seg_data[5]~107 SEG_DATA[5] } "NODE_NAME" } "" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "5 8 " "Info: Average interconnect usage is 5% of the available device resources. Peak interconnect usage is 8%" {  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:02 " "Info: Fitter routing operations ending: elapsed time is 00:00:02" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_NOT_USED" "" "Info: The Fitter performed an Auto Fit compilation.  No optimizations were skipped because the design's timing and routability requirements required full optimization." {  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  No optimizations were skipped because the design's timing and routability requirements required full optimization." 0 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "1 " "Warning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SEG_DATA\[0\] VCC " "Info: Pin SEG_DATA\[0\] has VCC driving its datain port" {  } { { "F.bdf" "" { Schematic "F:/数字频率计1/F.bdf" { { 24 864 1041 40 "SEG_DATA\[7..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "SEG_DATA\[0\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "plj" "UNKNOWN" "V1" "F:/数字频率计1/db/plj.quartus_db" { Floorplan "F:/数字频率计1/" "" "" { SEG_DATA[0] } "NODE_NAME" } "" } } { "F:/数字频率计1/plj.fld" "" { Floorplan "F:/数字频率计1/plj.fld" "" "" { SEG_DATA[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Jan 10 14:37:23 2009 " "Info: Processing ended: Sat Jan 10 14:37:23 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Info: Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}