plj.tan.qmsg

基于CPLD的数字频率计

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "CLKIN 32 " "Warning: Circuit may not operate. Detected 32 non-operational path(s) clocked by clock \"CLKIN\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "KZ:inst1\|dataout_buff\[6\] REG32B:inst2\|DOUT\[6\] CLKIN 5.138 ns " "Info: Found hold time violation between source  pin or register \"KZ:inst1\|dataout_buff\[6\]\" and destination pin or register \"REG32B:inst2\|DOUT\[6\]\" for clock \"CLKIN\" (Hold time is 5.138 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "6.514 ns + Largest " "Info: + Largest clock skew is 6.514 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLKIN destination 13.850 ns + Longest register " "Info: + Longest clock path from clock \"CLKIN\" to destination register is 13.850 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns CLKIN 1 CLK PIN_127 113 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 113; CLK Node = 'CLKIN'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "plj" "UNKNOWN" "V1" "F:/数字频率计1/db/plj.quartus_db" { Floorplan "F:/数字频率计1/" "" "" { CLKIN } "NODE_NAME" } "" } } { "F.bdf" "" { Schematic "F:/数字频率计1/F.bdf" { { -456 48 216 -440 "CLKIN" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.286 ns) + CELL(1.294 ns) 7.712 ns TESTCTL:inst17\|CLK2 2 REG LC_X12_Y3_N4 3 " "Info: 2: + IC(5.286 ns) + CELL(1.294 ns) = 7.712 ns; Loc. = LC_X12_Y3_N4; Fanout = 3; REG Node = 'TESTCTL:inst17\|CLK2'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "plj" "UNKNOWN" "V1" "F:/数字频率计1/db/plj.quartus_db" { Floorplan "F:/数字频率计1/" "" "6.580 ns" { CLKIN TESTCTL:inst17|CLK2 } "NODE_NAME" } "" } } { "TESTCTL.vhd" "" { Text "F:/数字频率计1/TESTCTL.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.887 ns) + CELL(1.294 ns) 9.893 ns TESTCTL:inst17\|DIV2CLK 3 REG LC_X12_Y3_N1 66 " "Info: 3: + IC(0.887 ns) + CELL(1.294 ns) = 9.893 ns; Loc. = LC_X12_Y3_N1; Fanout = 66; REG Node = 'TESTCTL:inst17\|DIV2CLK'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "plj" "UNKNOWN" "V1" "F:/数字频率计1/db/plj.quartus_db" { Floorplan "F:/数字频率计1/" "" "2.181 ns" { TESTCTL:inst17|CLK2 TESTCTL:inst17|DIV2CLK } "NODE_NAME" } "" } } { "TESTCTL.vhd" "" { Text "F:/数字频率计1/TESTCTL.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!