plj.fit.eqn

基于CPLD的数字频率计

E1L15_cout_1 = E1_cnt_scan[4] & (!E1L12);
E1L15 = CARRY(E1L15_cout_1);


--E1_cnt_scan[5] is XIANSHI:inst3|cnt_scan[5] at LC_X12_Y10_N9
--operation mode is arithmetic

E1_cnt_scan[5]_carry_eqn = (!E1L3 & E1L14) # (E1L3 & E1L15);
E1_cnt_scan[5]_lut_out = E1_cnt_scan[5] $ E1_cnt_scan[5]_carry_eqn;
E1_cnt_scan[5] = DFFEAS(E1_cnt_scan[5]_lut_out, GLOBAL(CLKIN), RST, , , , , , );

--E1L17 is XIANSHI:inst3|cnt_scan[5]~121 at LC_X12_Y10_N9
--operation mode is arithmetic

E1L17 = CARRY(!E1L15 # !E1_cnt_scan[5]);


--E1_cnt_scan[6] is XIANSHI:inst3|cnt_scan[6] at LC_X13_Y10_N0
--operation mode is arithmetic

E1_cnt_scan[6]_carry_eqn = E1L17;
E1_cnt_scan[6]_lut_out = E1_cnt_scan[6] $ !E1_cnt_scan[6]_carry_eqn;
E1_cnt_scan[6] = DFFEAS(E1_cnt_scan[6]_lut_out, GLOBAL(CLKIN), RST, , , , , , );

--E1L19 is XIANSHI:inst3|cnt_scan[6]~125 at LC_X13_Y10_N0
--operation mode is arithmetic

E1L19_cout_0 = E1_cnt_scan[6] & !E1L17;
E1L19 = CARRY(E1L19_cout_0);

--E1L20 is XIANSHI:inst3|cnt_scan[6]~125COUT1_150 at LC_X13_Y10_N0
--operation mode is arithmetic

E1L20_cout_1 = E1_cnt_scan[6] & !E1L17;
E1L20 = CARRY(E1L20_cout_1);


--E1_cnt_scan[7] is XIANSHI:inst3|cnt_scan[7] at LC_X13_Y10_N1
--operation mode is arithmetic

E1_cnt_scan[7]_carry_eqn = (!E1L17 & E1L19) # (E1L17 & E1L20);
E1_cnt_scan[7]_lut_out = E1_cnt_scan[7] $ E1_cnt_scan[7]_carry_eqn;
E1_cnt_scan[7] = DFFEAS(E1_cnt_scan[7]_lut_out, GLOBAL(CLKIN), RST, , , , , , );

--E1L22 is XIANSHI:inst3|cnt_scan[7]~129 at LC_X13_Y10_N1
--operation mode is arithmetic

E1L22_cout_0 = !E1L19 # !E1_cnt_scan[7];
E1L22 = CARRY(E1L22_cout_0);

--E1L23 is XIANSHI:inst3|cnt_scan[7]~129COUT1_152 at LC_X13_Y10_N1
--operation mode is arithmetic

E1L23_cout_1 = !E1L20 # !E1_cnt_scan[7];
E1L23 = CARRY(E1L23_cout_1);


--A1L29 is rtl~867 at LC_X12_Y10_N0
--operation mode is normal

A1L29 = E1_cnt_scan[4] & E1_cnt_scan[5] & E1_cnt_scan[6] & E1_cnt_scan[7];


--A1L30 is rtl~868 at LC_X12_Y10_N1
--operation mode is normal

A1L30 = E1_cnt_scan[9] & E1_cnt_scan[11] & E1_cnt_scan[8] & A1L29;


--A1L15 is rtl~1 at LC_X12_Y10_N2
--operation mode is normal

A1L15 = A1L28 & E1_cnt_scan[10] & (A1L30);


--A1L31 is rtl~869 at LC_X12_Y9_N9
--operation mode is normal

A1L31 = E1_en_xhdl3[0] & !E1_en_xhdl3[2] & A1L25 & !E1_en_xhdl3[1];


--A1L19 is rtl~5 at LC_X12_Y9_N3
--operation mode is normal

A1L19 = E1_en_xhdl3[3] & !E1_en_xhdl3[4] & A1L31;


--A1L32 is rtl~870 at LC_X11_Y9_N1
--operation mode is normal

A1L32 = E1_en_xhdl3[4] & !E1_en_xhdl3[3];


--A1L33 is rtl~871 at LC_X9_Y9_N8
--operation mode is normal

A1L33 = E1_en_xhdl3[0] & A1L26;


--A1L34 is rtl~872 at LC_X9_Y9_N4
--operation mode is normal

A1L34 = !E1_en_xhdl3[7] & (E1_en_xhdl3[5] & !E1_en_xhdl3[6]);


--A1L35 is rtl~873 at LC_X11_Y9_N8
--operation mode is normal

A1L35 = A1L34 & !A1L33 & (!A1L31 # !A1L32) # !A1L34 & (!A1L31 # !A1L32);


--A1L22 is rtl~8 at LC_X9_Y9_N6
--operation mode is normal

A1L22 = !E1_en_xhdl3[6] & E1_en_xhdl3[7] & !E1_en_xhdl3[5] & A1L33;


--A1L18 is rtl~4 at LC_X9_Y9_N9
--operation mode is normal

A1L18 = E1_en_xhdl3[6] & !E1_en_xhdl3[7] & !E1_en_xhdl3[5] & A1L33;


--A1L14 is rtl~0 at LC_X11_Y10_N9
--operation mode is normal

A1L14 = !E1_cnt_scan[10] & A1L28 & A1L30;


--E1L77 is XIANSHI:inst3|en_xhdl3[7]~1252 at LC_X10_Y9_N4
--operation mode is normal

E1L77 = !A1L18 & !A1L22 & A1L35 # !A1L14;


--E1L83 is XIANSHI:inst3|process1~0 at LC_X11_Y10_N3
--operation mode is normal

E1L83 = E1_cnt_scan[10] # !A1L30 # !E1L85 # !A1L28;


--A1L17 is rtl~3 at LC_X11_Y10_N0
--operation mode is normal

A1L17 = E1_en_xhdl3[0] & E1_en_xhdl3[2] & !E1_en_xhdl3[1] & A1L27;


--A1L16 is rtl~2 at LC_X11_Y10_N7
--operation mode is normal

A1L16 = E1_en_xhdl3[0] & !E1_en_xhdl3[2] & E1_en_xhdl3[1] & A1L27;


--E1L73 is XIANSHI:inst3|en_xhdl3[4]~1253 at LC_X11_Y10_N8
--operation mode is normal

E1L73 = E1L83 & (!A1L17 & !A1L16 # !A1L15);


--A1L24 is rtl~24 at LC_X10_Y9_N5
--operation mode is normal

A1L24 = A1L19 & A1L15 # !E1L73 # !E1L77;


--A1L21 is rtl~7 at LC_X9_Y10_N5
--operation mode is normal

A1L21 = A1L34 & A1L26 & E1_en_xhdl3[0];


--A1L20 is rtl~6 at LC_X12_Y9_N2
--operation mode is normal

A1L20 = E1_en_xhdl3[0] & A1L25 & E1L116 & A1L32;


--E1L78 is XIANSHI:inst3|en_xhdl3[7]~1257 at LC_X10_Y10_N4
--operation mode is normal

E1L78 = E1_en_xhdl3[4] # !E1_en_xhdl3[3] # !A1L31 # !A1L15;


--E1L71 is XIANSHI:inst3|en_xhdl3[3]~1259 at LC_X10_Y10_N7
--operation mode is normal

E1L71 = !E1L83 # !A1L17 # !A1L15;


--E1L79 is XIANSHI:inst3|en_xhdl3[7]~1261 at LC_X10_Y10_N9
--operation mode is normal

E1L79 = E1L77 & (!A1L17 & !A1L19 # !A1L15);


--E1L81 is XIANSHI:inst3|en_xhdl3~1264 at LC_X11_Y10_N4
--operation mode is normal

E1L81 = A1L15 & (A1L17 # A1L16 # A1L19);


--E1L82 is XIANSHI:inst3|en_xhdl3~1265 at LC_X11_Y10_N1
--operation mode is normal

E1L82 = A1L14 & (E1L85 # E1_en_xhdl3[0] & !A1L22) # !A1L14 & E1_en_xhdl3[0];


--A1L36 is rtl~874 at LC_X10_Y9_N6
--operation mode is normal

A1L36 = !A1L18 & A1L35;


--D1_DOUT[28] is REG32B:inst2|DOUT[28] at LC_X12_Y6_N8
--operation mode is normal

D1_DOUT[28]_lut_out = C1_dataout_buff[28];
D1_DOUT[28] = DFFEAS(D1_DOUT[28]_lut_out, !GLOBAL(F1_DIV2CLK), VCC, , A1L37, , , , );


--D1_DOUT[16] is REG32B:inst2|DOUT[16] at LC_X9_Y6_N8
--operation mode is normal

D1_DOUT[16]_lut_out = C1_dataout_buff[16];
D1_DOUT[16] = DFFEAS(D1_DOUT[16]_lut_out, !GLOBAL(F1_DIV2CLK), VCC, , A1L37, , , , );


--D1_DOUT[0] is REG32B:inst2|DOUT[0] at LC_X10_Y4_N9
--operation mode is normal

D1_DOUT[0]_lut_out = C1_dataout_buff[0];
D1_DOUT[0] = DFFEAS(D1_DOUT[0]_lut_out, !GLOBAL(F1_DIV2CLK), VCC, , A1L37, , , , );


--D1_DOUT[4] is REG32B:inst2|DOUT[4] at LC_X9_Y9_N3
--operation mode is normal

D1_DOUT[4]_lut_out = C1_dataout_buff[4];
D1_DOUT[4] = DFFEAS(D1_DOUT[4]_lut_out, !GLOBAL(F1_DIV2CLK), VCC, , A1L37, , , , );


--D1_DOUT[8] is REG32B:inst2|DOUT[8] at LC_X10_Y7_N9
--operation mode is normal

D1_DOUT[8]_lut_out = C1_dataout_buff[8];
D1_DOUT[8] = DFFEAS(D1_DOUT[8]_lut_out, !GLOBAL(F1_DIV2CLK), VCC, , A1L37, , , , );


--D1_DOUT[12] is REG32B:inst2|DOUT[12] at LC_X9_Y7_N9
--operation mode is normal

D1_DOUT[12]_lut_out = C1_dataout_buff[12];
D1_DOUT[12] = DFFEAS(D1_DOUT[12]_lut_out, !GLOBAL(F1_DIV2CLK), VCC, , A1L37, , , , );


--D1_DOUT[24] is REG32B:inst2|DOUT[24] at LC_X10_Y6_N5
--operation mode is normal

D1_DOUT[24]_lut_out = C1_dataout_buff[24];
D1_DOUT[24] = DFFEAS(D1_DOUT[24]_lut_out, !GLOBAL(F1_DIV2CLK), VCC, , A1L37, , , , );


--D1_DOUT[20] is REG32B:inst2|DOUT[20] at LC_X11_Y6_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

D1_DOUT[20]_lut_out = GND;
D1_DOUT[20] = DFFEAS(D1_DOUT[20]_lut_out, !GLOBAL(F1_DIV2CLK), VCC, , A1L37, C1_dataout_buff[20], , , VCC);


--D1_DOUT[29] is REG32B:inst2|DOUT[29] at LC_X11_Y6_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

D1_DOUT[29]_lut_out = GND;
D1_DOUT[29] = DFFEAS(D1_DOUT[29]_lut_out, !GLOBAL(F1_DIV2CLK), VCC, , A1L37, C1_dataout_buff[29], , , VCC);


--D1_DOUT[17] is REG32B:inst2|DOUT[17] at LC_X10_Y6_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

D1_DOUT[17]_lut_out = GND;
D1_DOUT[17] = DFFEAS(D1_DOUT[17]_lut_out, !GLOBAL(F1_DIV2CLK), VCC, , A1L37, C1_dataout_buff[17], , , VCC);


--D1_DOUT[1] is REG32B:inst2|DOUT[1] at LC_X9_Y7_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

D1_DOUT[1]_lut_out = GND;
D1_DOUT[1] = DFFEAS(D1_DOUT[1]_lut_out, !GLOBAL(F1_DIV2CLK), VCC, , A1L37, C1_dataout_buff[1], , , VCC);


--D1_DOUT[5] is REG32B:inst2|DOUT[5] at LC_X11_Y7_N2
--operation mode is normal

D1_DOUT[5]_lut_out = C1_dataout_buff[5];
D1_DOUT[5] = DFFEAS(D1_DOUT[5]_lut_out, !GLOBAL(F1_DIV2CLK), VCC, , A1L37, , , , );


--D1_DOUT[9] is REG32B:inst2|DOUT[9] at LC_X10_Y6_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

D1_DOUT[9]_lut_out = GND;
D1_DOUT[9] = DFFEAS(D1_DOUT[9]_lut_out, !GLOBAL(F1_DIV2CLK), VCC, , A1L37, C1_dataout_buff[9], , , VCC);


--D1_DOUT[13] is REG32B:inst2|DOUT[13] at LC_X10_Y7_N3
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

D1_DOUT[13]_lut_out = GND;
D1_DOUT[13] = DFFEAS(D1_DOUT[13]_lut_out, !GLOBAL(F1_DIV2CLK), VCC, , A1L37, C1_dataout_buff[13], , , VCC);


--D1_DOUT[25] is REG32B:inst2|DOUT[25] at LC_X12_Y4_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

D1_DOUT[25]_lut_out = GND;
D1_DOUT[25] = DFFEAS(D1_DOUT[25]_lut_out, !GLOBAL(F1_DIV2CLK), VCC, , A1L37, C1_dataout_buff[25], , , VCC);


--D1_DOUT[21] is REG32B:inst2|DOUT[21] at LC_X10_Y7_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

D1_DOUT[21]_lut_out = GND;
D1_DOUT[21] = DFFEAS(D1_DOUT[21]_lut_out, !GLOBAL(F1_DIV2CLK), VCC, , A1L37, C1_dataout_buff[21], , , VCC);


--D1_DOUT[30] is REG32B:inst2|DOUT[30] at LC_X12_Y6_N2
--operation mode is normal

D1_DOUT[30]_lut_out = C1_dataout_buff[30];
D1_DOUT[30] = DFFEAS(D1_DOUT[30]_lut_out, !GLOBAL(F1_DIV2CLK), VCC, , A1L37, , , , );


--D1_DOUT[18] is REG32B:inst2|DOUT[18] at LC_X8_Y8_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

D1_DOUT[18]_lut_out = GND;
D1_DOUT[18] = DFFEAS(D1_DOUT[18]_lut_out, !GLOBAL(F1_DIV2CLK), VCC, , A1L37, C1_dataout_buff[18], , , VCC);


--D1_DOUT[2] is REG32B:inst2|DOUT[2] at LC_X10_Y4_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

D1_DOUT[2]_lut_out = GND;
D1_DOUT[2] = DFFEAS(D1_DOUT[2]_lut_out, !GLOBAL(F1_DIV2CLK), VCC, , A1L37, C1_dataout_buff[2], , , VCC);


--D1_DOUT[6] is REG32B:inst2|DOUT[6] at LC_X9_Y6_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

D1_DOUT[6]_lut_out = GND;
D1_DOUT[6] = DFFEAS(D1_DOUT[6]_lut_out, !GLOBAL(F1_DIV2CLK), VCC, , A1L37, C1_dataout_buff[6], , , VCC);


--D1_DOUT[10] is REG32B:inst2|DOUT[10] at LC_X9_Y9_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

D1_DOUT[10]_lut_out = GND;
D1_DOUT[10] = DFFEAS(D1_DOUT[10]_lut_out, !GLOBAL(F1_DIV2CLK), VCC, , A1L37, C1_dataout_buff[10], , , VCC);


--D1_DOUT[14] is REG32B:inst2|DOUT[14] at LC_X8_Y8_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

D1_DOUT[14]_lut_out = GND;
D1_DOUT[14] = DFFEAS(D1_DOUT[14]_lut_out, !GLOBAL(F1_DIV2CLK), VCC, , A1L37, C1_dataout_buff[14], , , VCC);


--D1_DOUT[26] is REG32B:inst2|DOUT[26] at LC_X12_Y4_N3
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

D1_DOUT[26]_lut_out = GND;
D1_DOUT[26] = DFFEAS(D1_DOUT[26]_lut_out, !GLOBAL(F1_DIV2CLK), VCC, , A1L37, C1_dataout_buff[26], , , VCC);


--D1_DOUT[22] is REG32B:inst2|DOUT[22] at LC_X11_Y6_N3
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

D1_DOUT[22]_lut_out = GND;
D1_DOUT[22] = DFFEAS(D1_DOUT[22]_lut_out, !GLOBAL(F1_DIV2CLK), VCC, , A1L37, C1_dataout_buff[22], , , VCC);