📄 plj.fit.rpt
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; Number of Logic Elements (Average = 8.66) ; Number of LABs (Total = 35) ;
+--------------------------------------------+------------------------------+
; 1 ; 1 ;
; 2 ; 0 ;
; 3 ; 1 ;
; 4 ; 2 ;
; 5 ; 1 ;
; 6 ; 1 ;
; 7 ; 1 ;
; 8 ; 0 ;
; 9 ; 7 ;
; 10 ; 21 ;
+--------------------------------------------+------------------------------+
+-------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+------------------------------+
; LAB-wide Signals (Average = 1.57) ; Number of LABs (Total = 35) ;
+------------------------------------+------------------------------+
; 1 Async. clear ; 9 ;
; 1 Clock ; 16 ;
; 1 Clock enable ; 16 ;
; 2 Clocks ; 14 ;
+------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+------------------------------+
; Number of Signals Sourced (Average = 8.86) ; Number of LABs (Total = 35) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 1 ;
; 2 ; 0 ;
; 3 ; 1 ;
; 4 ; 2 ;
; 5 ; 1 ;
; 6 ; 1 ;
; 7 ; 0 ;
; 8 ; 1 ;
; 9 ; 7 ;
; 10 ; 18 ;
; 11 ; 1 ;
; 12 ; 1 ;
; 13 ; 1 ;
+---------------------------------------------+------------------------------+
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out (Average = 5.66) ; Number of LABs (Total = 35) ;
+-------------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 1 ;
; 2 ; 2 ;
; 3 ; 9 ;
; 4 ; 6 ;
; 5 ; 0 ;
; 6 ; 3 ;
; 7 ; 2 ;
; 8 ; 3 ;
; 9 ; 5 ;
; 10 ; 3 ;
; 11 ; 1 ;
+-------------------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 9.14) ; Number of LABs (Total = 35) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 5 ;
; 4 ; 2 ;
; 5 ; 0 ;
; 6 ; 4 ;
; 7 ; 6 ;
; 8 ; 3 ;
; 9 ; 1 ;
; 10 ; 1 ;
; 11 ; 2 ;
; 12 ; 1 ;
; 13 ; 1 ;
; 14 ; 3 ;
; 15 ; 2 ;
; 16 ; 2 ;
; 17 ; 1 ;
; 18 ; 0 ;
; 19 ; 0 ;
; 20 ; 1 ;
+---------------------------------------------+------------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Sat Jan 10 14:37:14 2009
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off plj -c plj
Info: Selected device EPM1270GT144C5 for design "plj"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info: Device EPM570GT144C5 is compatible
Info: Device EPM570GT144I5 is compatible
Info: Device EPM1270GT144I5 is compatible
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1000 MHz
Info: Assuming a global tsu requirement of 2.0 ns
Info: Assuming a global tco requirement of 1.0 ns
Info: Assuming a global tpd requirement of 1.0 ns
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "CLKIN" to use Global clock
Info: Pin "CLKIN" drives global clock, but is not placed in a dedicated clock pin position
Info: Automatically promoted some destinations of signal "TESTCTL:inst17|DIV2CLK" to use Global clock
Info: Destination "TESTCTL:inst17|DIV2CLK" may be non-global or may not use global clock
Info: Destination "CNT10:inst10|CQI[3]" may be non-global or may not use global clock
Info: Destination "CNT10:inst10|CQI[0]" may be non-global or may not use global clock
Info: Destination "CNT10:inst10|CQI[2]" may be non-global or may not use global clock
Info: Destination "CNT10:inst10|CQI[1]" may be non-global or may not use global clock
Info: Destination "CNT10:inst|CQI[0]" may be non-global or may not use global clock
Info: Destination "CNT10:inst9|CQI[3]" may be non-global or may not use global clock
Info: Destination "CNT10:inst9|CQI[0]" may be non-global or may not use global clock
Info: Destination "CNT10:inst9|CQI[2]" may be non-global or may not use global clock
Info: Destination "CNT10:inst9|CQI[1]" may be non-global or may not use global clock
Info: Limited to 10 non-global destinations
Info: Automatical
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