📄 plj.fit.talkback.xml
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<fast_output_connection>no</fast_output_connection>
<location_assigned_by>User</location_assigned_by>
<load units="pF">10</load>
</row>
<row>
<name>SEG_DATA[5]</name>
<pin__>111</pin__>
<i_o_bank>2</i_o_bank>
<x_coordinate>15</x_coordinate>
<y_coordinate>11</y_coordinate>
<cell_number>0</cell_number>
<output_register>no</output_register>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>16mA</current_strength>
<fast_output_connection>no</fast_output_connection>
<location_assigned_by>User</location_assigned_by>
<load units="pF">10</load>
</row>
<row>
<name>SEG_DATA[6]</name>
<pin__>108</pin__>
<i_o_bank>3</i_o_bank>
<x_coordinate>17</x_coordinate>
<y_coordinate>10</y_coordinate>
<cell_number>4</cell_number>
<output_register>no</output_register>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>16mA</current_strength>
<fast_output_connection>no</fast_output_connection>
<location_assigned_by>User</location_assigned_by>
<load units="pF">10</load>
</row>
<row>
<name>SEG_DATA[7]</name>
<pin__>109</pin__>
<i_o_bank>2</i_o_bank>
<x_coordinate>16</x_coordinate>
<y_coordinate>11</y_coordinate>
<cell_number>1</cell_number>
<output_register>no</output_register>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>16mA</current_strength>
<fast_output_connection>no</fast_output_connection>
<location_assigned_by>User</location_assigned_by>
<load units="pF">10</load>
</row>
</output_pins>
<i_o_bank_usage>
<row>
<i_o_bank>1</i_o_bank>
<usage>0 / 26 ( 0 % )</usage>
<vccio_voltage>3.3V</vccio_voltage>
</row>
<row>
<i_o_bank>2</i_o_bank>
<usage>17 / 30 ( 57 % )</usage>
<vccio_voltage>3.3V</vccio_voltage>
</row>
<row>
<i_o_bank>3</i_o_bank>
<usage>1 / 30 ( 3 % )</usage>
<vccio_voltage>3.3V</vccio_voltage>
</row>
<row>
<i_o_bank>4</i_o_bank>
<usage>1 / 30 ( 3 % )</usage>
<vccio_voltage>3.3V</vccio_voltage>
</row>
</i_o_bank_usage>
<advanced_data___general>
<row>
<name>Status Code</name>
<value>0</value>
</row>
<row>
<name>Desired User Slack</name>
<value>0</value>
</row>
<row>
<name>Fit Attempts</name>
<value>1</value>
</row>
</advanced_data___general>
<advanced_data___placement_preparation>
<row>
<name>Auto Fit Point 1 - Fit Attempt 1</name>
<value>ff</value>
</row>
<row>
<name>Mid Wire Use - Fit Attempt 1</name>
<value>14</value>
</row>
<row>
<name>Mid Slack - Fit Attempt 1</name>
<value>-35064</value>
</row>
<row>
<name>Internal Atom Count - Fit Attempt 1</name>
<value>297</value>
</row>
<row>
<name>LE/ALM Count - Fit Attempt 1</name>
<value>297</value>
</row>
<row>
<name>LAB Count - Fit Attempt 1</name>
<value>41</value>
</row>
<row>
<name>Outputs per Lab - Fit Attempt 1</name>
<value>5.220</value>
</row>
<row>
<name>Inputs per LAB - Fit Attempt 1</name>
<value>7.463</value>
</row>
<row>
<name>Global Inputs per LAB - Fit Attempt 1</name>
<value>1.024</value>
</row>
<row>
<name>LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1</name>
<value>0:36;1:3;2:2</value>
</row>
<row>
<name>LAB Constraint 'ce + sync load' - Fit Attempt 1</name>
<value>0:26;1:12;2:3</value>
</row>
<row>
<name>LAB Constraint 'non-global controls' - Fit Attempt 1</name>
<value>0:19;1:17;2:1;3:1;4:1;5:2</value>
</row>
<row>
<name>LAB Constraint 'un-route combination' - Fit Attempt 1</name>
<value>0:20;1:16;2:2;3:3</value>
</row>
<row>
<name>LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1</name>
<value>0:19;1:17;2:1;3:1;4:1;5:2</value>
</row>
<row>
<name>LAB Constraint 'un-route with async_clear' - Fit Attempt 1</name>
<value>0:20;1:16;2:2;3:3</value>
</row>
<row>
<name>LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1</name>
<value>0:30;1:11</value>
</row>
<row>
<name>LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1</name>
<value>0:41</value>
</row>
<row>
<name>LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1</name>
<value>0:25;1:15;2:1</value>
</row>
<row>
<name>LAB Constraint 'global control signals' - Fit Attempt 1</name>
<value>0:9;1:22;2:10</value>
</row>
<row>
<name>LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1</name>
<value>0:6;1:21;2:14</value>
</row>
<row>
<name>LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1</name>
<value>0:41</value>
</row>
<row>
<name>LAB Constraint 'aload_aclr pair' - Fit Attempt 1</name>
<value>0:6;1:32;2:3</value>
</row>
<row>
<name>LAB Constraint 'sload_sclear pair' - Fit Attempt 1</name>
<value>0:37;1:4</value>
</row>
<row>
<name>LAB Constraint 'invert_a constraint' - Fit Attempt 1</name>
<value>0:11;1:30</value>
</row>
<row>
<name>LAB Constraint 'has placement constraint' - Fit Attempt 1</name>
<value>0:36;1:5</value>
</row>
<row>
<name>LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1</name>
<value>0:41</value>
</row>
<row>
<name>LEs in Chains - Fit Attempt 1</name>
<value>39</value>
</row>
<row>
<name>LEs in Long Chains - Fit Attempt 1</name>
<value>39</value>
</row>
<row>
<name>LABs with Chains - Fit Attempt 1</name>
<value>5</value>
</row>
<row>
<name>LABs with Multiple Chains - Fit Attempt 1</name>
<value>0</value>
</row>
<row>
<name>Time - Fit Attempt 1</name>
<value>0</value>
</row>
<row>
<name>Time in tsm_tan.dll - Fit Attempt 1</name>
<value>0.016</value>
</row>
</advanced_data___placement_preparation>
<advanced_data___placement>
<row>
<name>Auto Fit Point 2 - Fit Attempt 1</name>
<value>ff</value>
</row>
<row>
<name>Early Wire Use - Fit Attempt 1</name>
<value>4</value>
</row>
<row>
<name>Early Slack - Fit Attempt 1</name>
<value>-59035</value>
</row>
<row>
<name>Auto Fit Point 3 - Fit Attempt 1</name>
<value>ff</value>
</row>
<row>
<name>Auto Fit Point 4 - Fit Attempt 1</name>
<value>ff</value>
</row>
<row>
<name>Mid Wire Use - Fit Attempt 1</name>
<value>7</value>
</row>
<row>
<name>Mid Slack - Fit Attempt 1</name>
<value>-51611</value>
</row>
<row>
<name>Late Wire Use - Fit Attempt 1</name>
<value>8</value>
</row>
<row>
<name>Late Slack - Fit Attempt 1</name>
<value>-51611</value>
</row>
<row>
<name>Auto Fit Point 5 - Fit Attempt 1</name>
<value>ff</value>
</row>
<row>
<name>Time - Fit Attempt 1</name>
<value>0</value>
</row>
<row>
<name>Time in tsm_tan.dll - Fit Attempt 1</name>
<value>0.236</value>
</row>
</advanced_data___placement>
<advanced_data___routing>
<row>
<name>Early Slack - Fit Attempt 1</name>
<value>-47988</value>
</row>
<row>
<name>Early Wire Use - Fit Attempt 1</name>
<value>7</value>
</row>
<row>
<name>Peak Regional Wire - Fit Attempt 1</name>
<value>10</value>
</row>
<row>
<name>Mid Slack - Fit Attempt 1</name>
<value>-55761</value>
</row>
<row>
<name>Late Slack - Fit Attempt 1</name>
<value>-54771</value>
</row>
<row>
<name>Late Slack - Fit Attempt 1</name>
<value>-54771</value>
</row>
<row>
<name>Late Wire Use - Fit Attempt 1</name>
<value>9</value>
</row>
<row>
<name>Time - Fit Attempt 1</name>
<value>1</value>
</row>
<row>
<name>Time in tsm_tan.dll - Fit Attempt 1</name>
<value>0.390</value>
</row>
</advanced_data___routing>
<files>
<top>F:/数字频率计1/F.bdf</top>
<extensions>
<ext filename="plj">1</ext>
<ext ext_name="vhd">8</ext>
<ext ext_name="bdf">1</ext>
</extensions>
<sub_files>
<sub_file>plj</sub_file>
<sub_file>F:/数字频率计1/CNT10.vhd</sub_file>
<sub_file>F:/数字频率计1/REG32B.vhd</sub_file>
<sub_file>F:/数字频率计1/TESTCTL.vhd</sub_file>
<sub_file>F:/数字频率计1/FREQ.vhd</sub_file>
<sub_file>F:/数字频率计1/F.bdf</sub_file>
<sub_file>F:/数字频率计1/kz.vhd</sub_file>
<sub_file>xinashi.vhd</sub_file>
<sub_file>F:/数字频率计1/xiANshi.vhd</sub_file>
<sub_file>F:/数字频率计1/FENPIN.vhd</sub_file>
</sub_files>
</files>
<architecture>
<family>MAX II</family>
<auto_device>OFF</auto_device>
<device>EPM1270GT144C5</device>
</architecture>
<pkg_io>
<pin_std count="19">LVTTL</pin_std>
</pkg_io>
<research>
<le_sclr>0</le_sclr>
<le_aclr>178</le_aclr>
<le_aload>0</le_aload>
<le_sload>26</le_sload>
<le_inverta>0</le_inverta>
<le_carry_in>30</le_carry_in>
<le_ce>64</le_ce>
<le_clk>178</le_clk>
<le_ce_sload>10</le_ce_sload>
<pin_sclr>0</pin_sclr>
<pin_aclr>0</pin_aclr>
<pin_ce_in>0</pin_ce_in>
<pin_ce_out>0</pin_ce_out>
</research>
</talkback>
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