plj.fit.talkback.xml

基于CPLD的数字频率计

		<setting>Normal</setting>
		<default_value>Normal</default_value>
	</row>
	<row>
		<option>Logic Cell Insertion - Logic Duplication</option>
		<setting>Auto</setting>
		<default_value>Auto</default_value>
	</row>
	<row>
		<option>Auto Register Duplication</option>
		<setting>Auto</setting>
		<default_value>Auto</default_value>
	</row>
	<row>
		<option>Auto Global Clock</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Global Register Control Signals</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Always Enable Input Buffers</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
</fitter_settings>
<fitter_device_options>
	<row>
		<option>Enable user-supplied start-up clock (CLKUSR)</option>
		<setting>Off</setting>
	</row>
	<row>
		<option>Enable device-wide reset (DEV_CLRn)</option>
		<setting>Off</setting>
	</row>
	<row>
		<option>Enable device-wide output enable (DEV_OE)</option>
		<setting>Off</setting>
	</row>
	<row>
		<option>Enable INIT_DONE output</option>
		<setting>Off</setting>
	</row>
	<row>
		<option>Configuration scheme</option>
		<setting>Passive Serial</setting>
	</row>
	<row>
		<option>Reserve all unused pins</option>
		<setting>As output driving ground</setting>
	</row>
	<row>
		<option>Base pin-out file on sameframe device</option>
		<setting>Off</setting>
	</row>
</fitter_device_options>
<input_pins>
	<row>
		<name>CLKIN</name>
		<pin__>127</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>9</x_coordinate>
		<y_coordinate>11</y_coordinate>
		<cell_number>3</cell_number>
		<combinational_fan_out>113</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>yes</global>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<location_assigned_by>User</location_assigned_by>
	</row>
	<row>
		<name>RST</name>
		<pin__>110</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>16</x_coordinate>
		<y_coordinate>11</y_coordinate>
		<cell_number>2</cell_number>
		<combinational_fan_out>20</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<location_assigned_by>User</location_assigned_by>
	</row>
	<row>
		<name>k</name>
		<pin__>71</pin__>
		<i_o_bank>4</i_o_bank>
		<x_coordinate>16</x_coordinate>
		<y_coordinate>0</y_coordinate>
		<cell_number>3</cell_number>
		<combinational_fan_out>32</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<location_assigned_by>User</location_assigned_by>
	</row>
</input_pins>
<output_pins>
	<row>
		<name>EN[0]</name>
		<pin__>134</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>7</x_coordinate>
		<y_coordinate>11</y_coordinate>
		<cell_number>2</cell_number>
		<output_register>no</output_register>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>16mA</current_strength>
		<fast_output_connection>no</fast_output_connection>
		<location_assigned_by>User</location_assigned_by>
		<load units="pF">10</load>
	</row>
	<row>
		<name>EN[1]</name>
		<pin__>133</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>7</x_coordinate>
		<y_coordinate>11</y_coordinate>
		<cell_number>1</cell_number>
		<output_register>no</output_register>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>16mA</current_strength>
		<fast_output_connection>no</fast_output_connection>
		<location_assigned_by>User</location_assigned_by>
		<load units="pF">10</load>
	</row>
	<row>
		<name>EN[2]</name>
		<pin__>124</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>9</x_coordinate>
		<y_coordinate>11</y_coordinate>
		<cell_number>1</cell_number>
		<output_register>no</output_register>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>16mA</current_strength>
		<fast_output_connection>no</fast_output_connection>
		<location_assigned_by>User</location_assigned_by>
		<load units="pF">10</load>
	</row>
	<row>
		<name>EN[3]</name>
		<pin__>123</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>9</x_coordinate>
		<y_coordinate>11</y_coordinate>
		<cell_number>0</cell_number>
		<output_register>no</output_register>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>16mA</current_strength>
		<fast_output_connection>no</fast_output_connection>
		<location_assigned_by>User</location_assigned_by>
		<load units="pF">10</load>
	</row>
	<row>
		<name>EN[4]</name>
		<pin__>121</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>10</x_coordinate>
		<y_coordinate>11</y_coordinate>
		<cell_number>1</cell_number>
		<output_register>no</output_register>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>16mA</current_strength>
		<fast_output_connection>no</fast_output_connection>
		<location_assigned_by>User</location_assigned_by>
		<load units="pF">10</load>
	</row>
	<row>
		<name>EN[5]</name>
		<pin__>125</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>9</x_coordinate>
		<y_coordinate>11</y_coordinate>
		<cell_number>2</cell_number>
		<output_register>no</output_register>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>16mA</current_strength>
		<fast_output_connection>no</fast_output_connection>
		<location_assigned_by>User</location_assigned_by>
		<load units="pF">10</load>
	</row>
	<row>
		<name>EN[6]</name>
		<pin__>131</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>8</x_coordinate>
		<y_coordinate>11</y_coordinate>
		<cell_number>2</cell_number>
		<output_register>no</output_register>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>16mA</current_strength>
		<fast_output_connection>no</fast_output_connection>
		<location_assigned_by>User</location_assigned_by>
		<load units="pF">10</load>
	</row>
	<row>
		<name>EN[7]</name>
		<pin__>132</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>7</x_coordinate>
		<y_coordinate>11</y_coordinate>
		<cell_number>0</cell_number>
		<output_register>no</output_register>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>16mA</current_strength>
		<fast_output_connection>no</fast_output_connection>
		<location_assigned_by>User</location_assigned_by>
		<load units="pF">10</load>
	</row>
	<row>
		<name>SEG_DATA[0]</name>
		<pin__>120</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>10</x_coordinate>
		<y_coordinate>11</y_coordinate>
		<cell_number>0</cell_number>
		<output_register>no</output_register>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>16mA</current_strength>
		<fast_output_connection>no</fast_output_connection>
		<location_assigned_by>User</location_assigned_by>
		<load units="pF">10</load>
	</row>
	<row>
		<name>SEG_DATA[1]</name>
		<pin__>119</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>11</x_coordinate>
		<y_coordinate>11</y_coordinate>
		<cell_number>3</cell_number>
		<output_register>no</output_register>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>16mA</current_strength>
		<fast_output_connection>no</fast_output_connection>
		<location_assigned_by>User</location_assigned_by>
		<load units="pF">10</load>
	</row>
	<row>
		<name>SEG_DATA[2]</name>
		<pin__>117</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>11</x_coordinate>
		<y_coordinate>11</y_coordinate>
		<cell_number>1</cell_number>
		<output_register>no</output_register>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>16mA</current_strength>
		<fast_output_connection>no</fast_output_connection>
		<location_assigned_by>User</location_assigned_by>
		<load units="pF">10</load>
	</row>
	<row>
		<name>SEG_DATA[3]</name>
		<pin__>114</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>12</x_coordinate>
		<y_coordinate>11</y_coordinate>
		<cell_number>1</cell_number>
		<output_register>no</output_register>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>16mA</current_strength>
		<fast_output_connection>yes</fast_output_connection>
		<location_assigned_by>User</location_assigned_by>
		<load units="pF">10</load>
	</row>
	<row>
		<name>SEG_DATA[4]</name>
		<pin__>113</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>13</x_coordinate>
		<y_coordinate>11</y_coordinate>
		<cell_number>1</cell_number>
		<output_register>no</output_register>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>16mA</current_strength>