plj.tan.talkback.xml

基于CPLD的数字频率计

<!--
This XML file (created on Mon Oct 27 21:45:08 2008) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature.  To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder.  For more information, go
to license.txt.
-->
<talkback>
<ver>6.0</ver>
<schema>quartus_version_6.0_build_178.xsd</schema>
<license>
	<host_id>00e0a00ac597</host_id>
	<nic_id>00e0a00ac597</nic_id>
	<cdrive_id>80087eed</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>6.0</version>
	<build>Build 178</build>
	<binary_type>32</binary_type>
	<module>quartus_tan</module>
	<edition>Full Version</edition>
	<eval>Licensed</eval>
	<compilation_end_time>Mon Oct 27 21:45:08 2008</compilation_end_time>
</tool>
<machine>
	<os>Windows XP</os>
	<cpu>
		<proc_count>1</proc_count>
		<cpu_freq units="MHz">1607</cpu_freq>
	</cpu>
	<ram units="MB">512</ram>
</machine>
<project>F:/数字频率计1/plj</project>
<revision>plj</revision>
<compilation_summary>
	<flow_status>Successful - Mon Oct 27 21:45:08 2008</flow_status>
	<quartus_ii_version>6.0 Build 178 04/27/2006 SJ Full Version</quartus_ii_version>
	<revision_name>plj</revision_name>
	<top_level_entity_name>F</top_level_entity_name>
	<family>MAX II</family>
	<device>EPM1270GT144C5</device>
	<timing_models>Final</timing_models>
	<met_timing_requirements>No</met_timing_requirements>
	<total_logic_elements>297 / 1,270 ( 23 % )</total_logic_elements>
	<total_pins>19 / 116 ( 16 % )</total_pins>
	<total_virtual_pins>0</total_virtual_pins>
	<ufm_blocks>0 / 1 ( 0 % )</ufm_blocks>
</compilation_summary>
<mep_data>
	<command_line>quartus_tan --read_settings_files=off --write_settings_files=off plj -c plj</command_line>
</mep_data>
<software_data>
	<smart_recompile>off</smart_recompile>
</software_data>
<messages>
	<warning>Warning: Circuit may not operate. Detected 117 non-operational path(s) clocked by clock &quot;CLKIN&quot; with clock skew larger than data delay. See Compilation Report for details.</warning>
	<warning>Warning: Found 38 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew</warning>
	<warning>Warning: Found pins functioning as undefined clocks and/or memory enables</warning>
	<info>Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings</info>
	<info>Info: Elapsed time: 00:00:03</info>
	<info>Info: Processing ended: Mon Oct 27 21:45:08 2008</info>
	<info>Info: th for register &quot;XIANSHI:inst3|DATAIN[29]&quot; (data pin = &quot;k&quot;, clock pin = &quot;CLKIN&quot;) is 1.078 ns</info>
	<info>Info: - Shortest pin to register delay is 6.487 ns</info>
</messages>
<clock_settings_summary>
	<row>
		<clock_node_name>CLKIN</clock_node_name>
		<type>User Pin</type>
		<fmax_requirement>None</fmax_requirement>
		<early_latency units="ns">0.000</early_latency>
		<late_latency units="ns">0.000</late_latency>
		<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
		<divide_base_fmax_by>N/A</divide_base_fmax_by>
		<offset>N/A</offset>
	</row>
</clock_settings_summary>
<performance>
	<nonclk>
		<type>Worst-case tsu</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>0.976 ns</actual>
	</nonclk>
	<nonclk>
		<type>Worst-case tco</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>23.381 ns</actual>
	</nonclk>
	<nonclk>
		<type>Worst-case th</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>1.078 ns</actual>
	</nonclk>
	<clk>
		<name>CLKIN</name>
		<slack>N/A</slack>
		<required>None</required>
		<actual>10.42 MHz ( period = 95.998 ns )</actual>
	</clk>
</performance>
</talkback>