tlc5510.tan.rpt

TI公司的TLC5510的用VHDL写的控制器及其仿真

; N/A   ; None         ; 10.670 ns  ; DATA[0]~reg0       ; DATA[0] ; CLK        ;
; N/A   ; None         ; 10.580 ns  ; DATA[6]~reg0       ; DATA[6] ; CLK        ;
; N/A   ; None         ; 10.480 ns  ; DATA[7]~reg0       ; DATA[7] ; CLK        ;
; N/A   ; None         ; 10.412 ns  ; DATA[4]~reg0       ; DATA[4] ; CLK        ;
; N/A   ; None         ; 10.236 ns  ; DATA[1]~reg0       ; DATA[1] ; CLK        ;
; N/A   ; None         ; 8.355 ns   ; STA_G_CURRENTSTATE ; DCLK    ; CLK        ;
; N/A   ; None         ; 8.355 ns   ; STA_G_CURRENTSTATE ; ADCLK   ; CLK        ;
+-------+--------------+------------+--------------------+---------+------------+


+------------------------------------------------------------+
; tpd                                                        ;
+-------+-------------------+-----------------+-------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From  ; To   ;
+-------+-------------------+-----------------+-------+------+
; N/A   ; None              ; 10.532 ns       ; CTLOE ; ADOE ;
+-------+-------------------+-----------------+-------+------+


+--------------------------------------------------------------------------+
; th                                                                       ;
+---------------+-------------+-----------+------+--------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To           ; To Clock ;
+---------------+-------------+-----------+------+--------------+----------+
; N/A           ; None        ; 4.490 ns  ; D[7] ; DATA[7]~reg0 ; CLK      ;
; N/A           ; None        ; 3.708 ns  ; D[5] ; DATA[5]~reg0 ; CLK      ;
; N/A           ; None        ; 2.793 ns  ; D[6] ; DATA[6]~reg0 ; CLK      ;
; N/A           ; None        ; -0.462 ns ; D[1] ; DATA[1]~reg0 ; CLK      ;
; N/A           ; None        ; -0.490 ns ; D[4] ; DATA[4]~reg0 ; CLK      ;
; N/A           ; None        ; -0.498 ns ; D[2] ; DATA[2]~reg0 ; CLK      ;
; N/A           ; None        ; -0.633 ns ; D[3] ; DATA[3]~reg0 ; CLK      ;
; N/A           ; None        ; -1.136 ns ; D[0] ; DATA[0]~reg0 ; CLK      ;
+---------------+-------------+-----------+------+--------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Mon May 04 11:08:11 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off tlc5510 -c tlc5510 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "STA_G_CURRENTSTATE" as buffer
Info: Clock "CLK" Internal fmax is restricted to 360.1 MHz between source register "STA_G_CURRENTSTATE" and destination register "STA_G_CURRENTSTATE"
    Info: fmax restricted to clock pin edge rate 2.777 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.501 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y6_N21; Fanout = 4; REG Node = 'STA_G_CURRENTSTATE'
            Info: 2: + IC(0.000 ns) + CELL(0.393 ns) = 0.393 ns; Loc. = LCCOMB_X1_Y6_N20; Fanout = 1; COMB Node = 'STA_G_CURRENTSTATE~2'
            Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 0.501 ns; Loc. = LCFF_X1_Y6_N21; Fanout = 4; REG Node = 'STA_G_CURRENTSTATE'
            Info: Total cell delay = 0.501 ns ( 100.00 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "CLK" to destination register is 3.554 ns
                Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_86; Fanout = 1; CLK Node = 'CLK'
                Info: 2: + IC(1.943 ns) + CELL(0.666 ns) = 3.554 ns; Loc. = LCFF_X1_Y6_N21; Fanout = 4; REG Node = 'STA_G_CURRENTSTATE'
                Info: Total cell delay = 1.611 ns ( 45.33 % )
                Info: Total interconnect delay = 1.943 ns ( 54.67 % )
            Info: - Longest clock path from clock "CLK" to source register is 3.554 ns
                Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_86; Fanout = 1; CLK Node = 'CLK'
                Info: 2: + IC(1.943 ns) + CELL(0.666 ns) = 3.554 ns; Loc. = LCFF_X1_Y6_N21; Fanout = 4; REG Node = 'STA_G_CURRENTSTATE'
                Info: Total cell delay = 1.611 ns ( 45.33 % )
                Info: Total interconnect delay = 1.943 ns ( 54.67 % )
        Info: + Micro clock to output delay of source is 0.304 ns
        Info: + Micro setup delay of destination is -0.040 ns
Info: tsu for register "DATA[0]~reg0" (data pin = "D[0]", clock pin = "CLK") is 1.402 ns
    Info: + Longest pin to register delay is 7.640 ns
        Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_104; Fanout = 1; PIN Node = 'D[0]'
        Info: 2: + IC(6.381 ns) + CELL(0.206 ns) = 7.532 ns; Loc. = LCCOMB_X13_Y13_N20; Fanout = 1; COMB Node = 'DATA[0]~reg0feeder'
        Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.640 ns; Loc. = LCFF_X13_Y13_N21; Fanout = 1; REG Node = 'DATA[0]~reg0'
        Info: Total cell delay = 1.259 ns ( 16.48 % )
        Info: Total interconnect delay = 6.381 ns ( 83.52 % )
    Info: + Micro setup delay of destination is -0.040 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 6.198 ns
        Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_86; Fanout = 1; CLK Node = 'CLK'
        Info: 2: + IC(1.943 ns) + CELL(0.970 ns) = 3.858 ns; Loc. = LCFF_X1_Y6_N21; Fanout = 4; REG Node = 'STA_G_CURRENTSTATE'
        Info: 3: + IC(0.817 ns) + CELL(0.000 ns) = 4.675 ns; Loc. = CLKCTRL_G1; Fanout = 8; COMB Node = 'STA_G_CURRENTSTATE~clkctrl'
        Info: 4: + IC(0.857 ns) + CELL(0.666 ns) = 6.198 ns; Loc. = LCFF_X13_Y13_N21; Fanout = 1; REG Node = 'DATA[0]~reg0'
        Info: Total cell delay = 2.581 ns ( 41.64 % )
        Info: Total interconnect delay = 3.617 ns ( 58.36 % )
Info: tco from clock "CLK" to destination pin "DATA[2]" through register "DATA[2]~reg0" is 13.197 ns
    Info: + Longest clock path from clock "CLK" to source register is 6.198 ns
        Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_86; Fanout = 1; CLK Node = 'CLK'
        Info: 2: + IC(1.943 ns) + CELL(0.970 ns) = 3.858 ns; Loc. = LCFF_X1_Y6_N21; Fanout = 4; REG Node = 'STA_G_CURRENTSTATE'
        Info: 3: + IC(0.817 ns) + CELL(0.000 ns) = 4.675 ns; Loc. = CLKCTRL_G1; Fanout = 8; COMB Node = 'STA_G_CURRENTSTATE~clkctrl'
        Info: 4: + IC(0.857 ns) + CELL(0.666 ns) = 6.198 ns; Loc. = LCFF_X24_Y11_N7; Fanout = 1; REG Node = 'DATA[2]~reg0'
        Info: Total cell delay = 2.581 ns ( 41.64 % )
        Info: Total interconnect delay = 3.617 ns ( 58.36 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 6.695 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X24_Y11_N7; Fanout = 1; REG Node = 'DATA[2]~reg0'
        Info: 2: + IC(3.629 ns) + CELL(3.066 ns) = 6.695 ns; Loc. = PIN_26; Fanout = 0; PIN Node = 'DATA[2]'
        Info: Total cell delay = 3.066 ns ( 45.80 % )
        Info: Total interconnect delay = 3.629 ns ( 54.20 % )
Info: Longest tpd from source pin "CTLOE" to destination pin "ADOE" is 10.532 ns
    Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_132; Fanout = 1; PIN Node = 'CTLOE'
    Info: 2: + IC(6.352 ns) + CELL(3.236 ns) = 10.532 ns; Loc. = PIN_133; Fanout = 0; PIN Node = 'ADOE'
    Info: Total cell delay = 4.180 ns ( 39.69 % )
    Info: Total interconnect delay = 6.352 ns ( 60.31 % )
Info: th for register "DATA[7]~reg0" (data pin = "D[7]", clock pin = "CLK") is 4.490 ns
    Info: + Longest clock path from clock "CLK" to destination register is 6.170 ns
        Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_86; Fanout = 1; CLK Node = 'CLK'
        Info: 2: + IC(1.943 ns) + CELL(0.970 ns) = 3.858 ns; Loc. = LCFF_X1_Y6_N21; Fanout = 4; REG Node = 'STA_G_CURRENTSTATE'
        Info: 3: + IC(0.817 ns) + CELL(0.000 ns) = 4.675 ns; Loc. = CLKCTRL_G1; Fanout = 8; COMB Node = 'STA_G_CURRENTSTATE~clkctrl'
        Info: 4: + IC(0.829 ns) + CELL(0.666 ns) = 6.170 ns; Loc. = LCFF_X27_Y7_N1; Fanout = 1; REG Node = 'DATA[7]~reg0'
        Info: Total cell delay = 2.581 ns ( 41.83 % )
        Info: Total interconnect delay = 3.589 ns ( 58.17 % )
    Info: + Micro hold delay of destination is 0.306 ns
    Info: - Shortest pin to register delay is 1.986 ns
        Info: 1: + IC(0.000 ns) + CELL(1.110 ns) = 1.110 ns; Loc. = PIN_90; Fanout = 1; PIN Node = 'D[7]'
        Info: 2: + IC(0.562 ns) + CELL(0.206 ns) = 1.878 ns; Loc. = LCCOMB_X27_Y7_N0; Fanout = 1; COMB Node = 'DATA[7]~reg0feeder'
        Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 1.986 ns; Loc. = LCFF_X27_Y7_N1; Fanout = 1; REG Node = 'DATA[7]~reg0'
        Info: Total cell delay = 1.424 ns ( 71.70 % )
        Info: Total interconnect delay = 0.562 ns ( 28.30 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Allocated 113 megabytes of memory during processing
    Info: Processing ended: Mon May 04 11:08:12 2009
    Info: Elapsed time: 00:00:01