beipin0.v

次代码利用verilog HDL来描述的

module beipin0(clk,ina,inb,dout);
input clk;
input ina,inb;
output dout;

reg b,c,d,e;
wire f,g;

always@(negedge clk)
  begin
    if(clk==0)
      begin
        b<=ina;
        c<=b;
      end
    else
      begin
        b<=b;
        c<=c;
      end
  end
always@(negedge clk)
  begin
    if(clk==0)
      begin
        d<=inb;
        e<=d;
      end
    else
      begin
        d<=d;
        e<=e;
      end
  end

assign f=b^c;
assign g=d^e;
assign dout=!(f^g);

endmodule