basic_gate.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY basic_gate IS 
           PORT (a  : IN  std_logic;
                 b  : IN  std_logic;
                 c1 : OUT std_logic;
                 c2 : OUT std_logic;
                 c3 : OUT std_logic;
                 c4 : OUT std_logic;
			     c5 : OUT std_logic);
END basic_gate;

ARCHITECTURE behave_arc OF basic_gate IS
BEGIN
     P1:PROCESS(a,b)
     BEGIN
	  c1 <= a OR b;
     END PROCESS P1;
     P2:PROCESS(a)
     BEGIN
	  c2 <= NOT a;
     END PROCESS P2;
     P3:PROCESS(a,b)
     BEGIN
	  c3 <= a NAND b;
     END PROCESS P3;
     P4:PROCESS(a,b)
     BEGIN
	  c4 <= a NOR b;
     END PROCESS P4;
     P5:PROCESS(a,b)
     BEGIN
	  c5 <= a XOR b;
     END PROCESS P5;
END behave_arc;