decoder8421_10.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY decoder8421_10 IS 
           PORT (a,b,c,d : IN  std_logic;
		 y  : OUT std_logic_vector(9 DOWNTO 0));
END decoder8421_10;

ARCHITECTURE rtl_arc OF decoder8421_10 IS
     SIGNAl  comb  : std_logic_vector(3 DOWNTO 0);
BEGIN
     comb <= d & c & b & a;
     PROCESS (comb)
     BEGIN
          CASE comb IS
               WHEN "0000" => y <= "0000000001";
               WHEN "0001" => y <= "0000000010";
               WHEN "0010" => y <= "0000000100";
               WHEN "0011" => y <= "0000001000";
               WHEN "0100" => y <= "0000010000";
               WHEN "0101" => y <= "0000100000";
               WHEN "0110" => y <= "0001000000";
               WHEN "0111" => y <= "0010000000";
               WHEN "1000" => y <= "0100000000";
               WHEN "1001" => y <= "1000000000";
               WHEN OTHERS => y  <= "XXXXXXXXXX";
          END CASE;
     END PROCESS;
END rtl_arc;