and3_gate.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY and3_gate IS 
           PORT (a  : IN  std_logic;
                 b  : IN  std_logic;
                 c  : IN  std_logic;
	         y  : OUT std_logic);
END and3_gate;

ARCHITECTURE rtl_arc OF and3_gate IS
BEGIN
PROCESS (a,b,c)
     VARIABLE  comb  : std_logic_vector(2 DOWNTO 0);
     BEGIN
          comb := a & b & c;
          CASE comb IS
               WHEN "000" => y <= '0';
               WHEN "001" => y <= '0';
               WHEN "010" => y <= '0';
               WHEN "011" => y <= '0';
               WHEN "100" => y <= '0';
               WHEN "101" => y <= '0';
               WHEN "110" => y <= '0';
               WHEN "111" => y <= '1';
               WHEN OTHERS => y <= 'X';
          END CASE;
     END PROCESS;
END rtl_arc;