and3_gate.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY and2_gate IS 
           PORT (a  : IN  std_logic;
                 b  : IN  std_logic;
		 c  : OUT std_logic);
END and2_gate;

ARCHITECTURE behave_arc OF and2_gate IS
BEGIN
     PROCESS(a,b)
     BEGIN
	  c <= a AND b;
     END PROCESS;
END behave_arc;	

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY and3_gate IS 
           PORT (a  : IN  std_logic;
                 b  : IN  std_logic;
                 c  : IN  std_logic;
	         y  : OUT std_logic);
END and3_gate;

ARCHITECTURE structure_arc OF and3_gate IS
         COMPONENT and2_gate
            PORT (a  : IN  std_logic;
                  b  : IN  std_logic;
		  c  : OUT std_logic);
         END COMPONENT;
     SIGNAL  tmp : std_logic;
BEGIN
         U1:and2_gate 
            PORT MAP (a,b,tmp);
	 U2:and2_gate
            PORT MAP (tmp,c,y);
END structure_arc;