encoder8_3.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY encoder8_3 IS 
           PORT (d  : IN  std_logic_vector(7 DOWNTO 0);
                 q  : OUT std_logic_vector(2 DOWNTO 0));
END encoder8_3;

ARCHITECTURE rtl_arc OF encoder8_3 IS
BEGIN
     PROCESS (d)
     BEGIN
          CASE d IS
               WHEN "01111111" => q <= "111";
               WHEN "10111111" => q <= "110";
               WHEN "11011111" => q <= "101";
               WHEN "11101111" => q <= "100";
               WHEN "11110111" => q <= "011";
               WHEN "11111011" => q <= "010";
               WHEN "11111101" => q <= "001";
               WHEN "11111110" => q <= "000";
               WHEN OTHERS => q  <= "ZZZ";
          END CASE;
     END PROCESS;
END rtl_arc;