counter.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY counter IS 
           PORT (clk       : IN  std_logic;
			     count_out : OUT integer);
END counter;

ARCHITECTURE count_255 OF counter IS
BEGIN
     P1: PROCESS (clk)
     VARIABLE  count_tmp  : integer :=0;
     BEGIN
          IF (clk'event AND clk ='1') THEN
              IF (count_tmp =255) THEN
                  count_tmp := 0;
              ELSE
                  count_tmp := count_tmp+1;
              END IF; 
          END IF;
          count_out <= count_tmp;
     END PROCESS P1;
END count_255;

ARCHITECTURE count_65535 OF counter IS
BEGIN
     P1: PROCESS (clk)
     VARIABLE  count_tmp  : integer :=0;
     BEGIN
          IF (clk'event AND clk ='1') THEN
              IF (count_tmp =65535) THEN
                  count_tmp := 0;
              ELSE
                  count_tmp := count_tmp+1;
              END IF; 
          END IF;
          count_out <= count_tmp;
     END PROCESS P1;
END count_65535;

CONFIGURATION small_counter OF counter IS
      FOR count_255
      END FOR;
END small_counter;

CONFIGURATION big_counter OF counter IS
      FOR count_65535
      END FOR;
END big_counter;