full_adder.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY half_adder IS 
       PORT ( A,B : IN  std_logic;
              Co  : OUT std_logic;
              S   : OUT std_logic);
END half_adder; 

ARCHITECTURE rtl OF half_adder IS
      SIGNAL tmp1,tmp2 : std_logic;
BEGIN
	     tmp1 <= A OR B;
	     tmp2 <= A NAND B;
	     Co  <= NOT tmp1;
	     S   <= tmp1 AND tmp2;
END rtl;

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY or_gate IS 
       PORT ( a,b : IN  std_logic;
              c   : OUT std_logic);
END or_gate; 

ARCHITECTURE rtl OF or_gate IS

BEGIN
	     c <= a AND b;
END rtl;

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY full_adder IS 
        PORT (A,B : IN  std_logic;
              Cin : IN  std_logic;
              Co  : OUT std_logic;
              S   : OUT std_logic);
END full_adder; 

ARCHITECTURE structure OF full_adder IS 
      SIGNAL tmp1,tmp2,tmp3 : std_logic;
      COMPONENT half_adder
            PORT(A,B : IN  std_logic;
                 Co  : OUT std_logic;
                 S   : OUT std_logic);
      END COMPONENT;
      COMPONENT or_gate
            PORT(a,b : IN  std_logic;
                 c   : OUT std_logic);
      END COMPONENT;
BEGIN
          U0:  half_adder
               PORT MAP(A,B,tmp1,tmp2);
          U1:  half_adder
               PORT MAP(tmp1,Cin,S,tmp3);
          U2:  or_gate
               PORT MAP(tmp3,tmp2,Co);
END structure;