full_adder.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY full_adder IS 
        PORT (A,B : IN  std_logic;
              Cin : IN  std_logic;
              Co  : OUT std_logic;
              S   : OUT std_logic);
END full_adder; 

ARCHITECTURE behave OF full_adder IS
BEGIN
         PROCESS(A,B,Cin)
	     VARIABLE  n  :  integer RANGE 0 TO 3;
	     CONSTANT  S_vector  : std_logic_vector(0 TO 3) :="0101";
	     CONSTANT  Co_vector : std_logic_vector(0 TO 3) :="0011";
         BEGIN
	          n := 0;
              IF (A ='1') THEN
		         n := n+1;
              END IF; 
	          IF (B ='1') THEN
		         n := n+1;
              END IF;
              IF (Cin ='1') THEN
		         n := n+1;
              END IF;
              S <= S_vector(n);
              Co <= Co_vector(n);
         END PROCESS;
END behave;