dff.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY dff IS
       GENERIC (setup_time,hold_time : time);
       PORT (d   : IN  std_logic;
             clk : IN  std_logic;
             q   : OUT std_logic);
       BEGIN
            setup_check: PROCESS(clk)
            BEGIN
                 IF (clk'event AND clk = '1') THEN
                     ASSERT(d'last_event >= setup_time)
                     REPORT "setup time error"
                     SEVERITY error;
                 END IF;
            END PROCESS setup_check;
            hold_check: PROCESS(clk'delayed(hold_time))
            BEGIN
                 IF (clk'delayed(hold_time)'event AND
                                 clk'delayed(hold_time)='1') THEN
                     ASSERT((d'last_event = 0 ns) OR
                                 (d'last_event >= hold_time))
                     REPORT "hold time error"
                     SEVERITY error;
                 END IF;
            END PROCESS hold_check;
END dff;

ARCHITECTURE rtl OF dff IS
BEGIN
     PROCESS (clk)
     BEGIN
          IF (clk'event AND clk = '1') THEN
              q <= d;
          END IF;
     END PROCESS;
END rtl;