and4.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY and_gate IS
           PORT (a,b  : IN  std_logic;
		   c  : OUT std_logic);
END and_gate;

ARCHITECTURE behave OF and_gate IS
BEGIN
             c <= a AND b;
END behave; 


LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
--USE WORK.gate.ALL;

ENTITY and4 IS 
           PORT (a,b,c,d  : IN  std_logic;
		       q  : OUT std_logic);
END and4;

ARCHITECTURE structural OF and4 IS
         COMPONENT and_gate
            PORT (a  : IN  std_logic;
                  b  : IN  std_logic;
		  c  : OUT std_logic);
         END COMPONENT;
         SIGNAL  q1,q2  : std_logic;
BEGIN
	     U1:and_gate PORT MAP (a,b,q1);
	     U2:and_gate PORT MAP (c,d,q2);
	     U3:and_gate PORT MAP (q1,q2,q);    
END structural;