full_adder.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY and_gate IS 
           PORT (a  : IN  std_logic;
                 b  : IN  std_logic;
		 c  : OUT std_logic);
END and_gate;
ARCHITECTURE and2_arc OF and_gate IS
BEGIN
     PROCESS (a,b)
     BEGIN
          c <= a AND b;
     END PROCESS;
END and2_arc;
CONFIGURATION and2_cfg OF and_gate IS
      FOR and2_arc
      END FOR;
END and2_cfg;

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY or_gate IS 
           PORT (a  : IN  std_logic;
                 b  : IN  std_logic;
		 c  : OUT std_logic);
END or_gate;
ARCHITECTURE or2_arc OF or_gate IS
BEGIN
     PROCESS (a,b)
     BEGIN
          c <= a OR b;
     END PROCESS;
END or2_arc;
CONFIGURATION or2_cfg OF or_gate IS
      FOR or2_arc
      END FOR;
END or2_cfg;

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY xor_gate IS 
           PORT (a  : IN  std_logic;
                 b  : IN  std_logic;
		 c  : OUT std_logic);
END xor_gate;
ARCHITECTURE xor2_arc OF xor_gate IS
BEGIN
     PROCESS (a,b)
     BEGIN
          c <= a XOR b;
     END PROCESS;
END xor2_arc;
CONFIGURATION xor2_cfg OF xor_gate IS
      FOR xor2_arc
      END FOR;
END xor2_cfg;

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
--USE WORK.gate.ALL;

ENTITY full_adder IS 
        PORT (A,B : IN  std_logic;
              Cin : IN  std_logic;
              Co  : OUT std_logic;
              S   : OUT std_logic);
END full_adder; 

ARCHITECTURE structure OF full_adder IS
         COMPONENT and_gate
            PORT (a  : IN  std_logic;
                  b  : IN  std_logic;
		  c  : OUT std_logic);
         END COMPONENT;
         COMPONENT or_gate
            PORT (a  : IN  std_logic;
                  b  : IN  std_logic;
		  c  : OUT std_logic);
         END COMPONENT;
         COMPONENT xor_gate
            PORT (a  : IN  std_logic;
                  b  : IN  std_logic;
		  c  : OUT std_logic);
         END COMPONENT;
         SIGNAL  tmp1,tmp2,tmp3  : std_logic;
BEGIN
	 U1:xor_gate PORT MAP (A,B,tmp1);
         U2:xor_gate PORT MAP (tmp1,Cin,S);
	 U3:and_gate PORT MAP (tmp1,Cin,tmp2);
         U4:and_gate PORT MAP (A,B,tmp3);
	 U5:or_gate  PORT MAP (tmp2,tmp3,Co);
END structure;