example.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY example IS 
           PORT (a  : IN  std_logic;
                 b  : IN  std_logic;
		 y  : OUT std_logic);
END example;

ARCHITECTURE and2_arc OF example IS
BEGIN
     PROCESS (a,b)
     VARIABLE  comb  : std_logic_vector(1 DOWNTO 0);
     BEGIN
          comb := a & b;
          CASE comb IS
               WHEN "00" => y <= '0';
               WHEN "01" => y <= '0';
               WHEN "10" => y <= '0';
               WHEN "11" => y <= '1';
               WHEN OTHERS => y <= 'X';
          END CASE;
     END PROCESS;
END and2_arc;	

ARCHITECTURE or2_arc OF example IS
BEGIN
     PROCESS (a,b)
     VARIABLE  comb  : std_logic_vector(1 DOWNTO 0);
     BEGIN
          comb := a & b;
          CASE comb IS
               WHEN "00" => y <= '0';
               WHEN "01" => y <= '1';
               WHEN "10" => y <= '1';
               WHEN "11" => y <= '1';
               WHEN OTHERS => y <= 'X';
          END CASE;
     END PROCESS;
END or2_arc;

ARCHITECTURE xor2_arc OF example IS
BEGIN
     PROCESS (a,b)
     VARIABLE  comb  : std_logic_vector(1 DOWNTO 0);
     BEGIN
          comb := a & b;
          CASE comb IS
               WHEN "00" => y <= '0';
               WHEN "01" => y <= '1';
               WHEN "10" => y <= '1';
               WHEN "11" => y <= '0';
               WHEN OTHERS => y <= 'X';
          END CASE;
     END PROCESS;
END xor2_arc;

CONFIGURATION and2_cfg OF example IS
      FOR and2_arc
      END FOR;
END and2_cfg;

CONFIGURATION or2_cfg OF example IS
      FOR or2_arc
      END FOR;
END or2_cfg;

CONFIGURATION xor2_cfg OF example IS
      FOR xor2_arc
      END FOR;
END xor2_cfg;