comparison.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;


ENTITY comparison IS 
           PORT (a  : IN  std_logic_vector(7 DOWNTO 0);
                 b  : IN  integer;
				 q  : OUT std_logic);
END comparison;

ARCHITECTURE rtl OF comparison IS
    FUNCTION vector_to_int
             (input  : IN  std_logic_vector) RETURN integer IS
             VARIABLE  result,temp  : integer := 0;
    BEGIN
             FOR i IN input'low TO input'high LOOP
                 temp := 0;
                 IF (input(i)= '1') THEN
                     temp := 2**(i- input'low);
                 ELSE
                     ASSERT (input(i)= '0')
                     REPORT "can not convert std_logic_vector to integer."
                     SEVERITY warning;
                 END IF;
                 result := result + temp;
             END LOOP;
             RETURN (result);
    END vector_to_int;
BEGIN
         P1:PROCESS(a,b)
         BEGIN
              IF (vector_to_int(a) > b) THEN
                  q <= '1';
              ELSE
                  q <= '0';
              END IF;
         END PROCESS P1;
END rtl;