full_adder.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY full_adder IS 
           PORT (A,B : IN  std_logic;
	         Cin : IN  std_logic;
	         Co  : OUT std_logic;
	         S   : OUT std_logic);
END full_adder;


ARCHITECTURE rtl OF full_adder IS
BEGIN
         example: BLOCK
              PORT (a_A   : IN  std_logic;
	            a_B   : IN  std_logic;
	            a_Cin : IN  std_logic;
	            a_Co  : OUT std_logic;
	            a_S   : OUT std_logic);
              PORT MAP (a_A => A,a_B => B,a_Cin => Cin,a_Co => Co,a_S => S);
              SIGNAL  tmp1,tmp2  : std_logic;
         BEGIN
              P1: PROCESS (a_A,a_B)
              BEGIN
                  tmp1 <= a_A XOR a_B;
              END PROCESS P1;

              P2: PROCESS (tmp1,a_Cin)
              BEGIN
                   tmp2 <= tmp1 AND a_Cin;
              END PROCESS P2;

              P3: PROCESS (tmp1,a_Cin)
              BEGIN
                  a_S <= tmp1 XOR a_Cin;
              END PROCESS P3;

              P4: PROCESS (a_A,a_B, tmp2)
              BEGIN
                   a_Co <= tmp2 OR (a_A AND a_B);
              END PROCESS P4;
         END BLOCK example;
END rtl;