cpu.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

PACKAGE bit32 IS
        TYPE tw32 IS ARRAY (31 DOWNTO 0) OF std_logic;
END bit32;

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE WORK.bit32.ALL;

ENTITY cpu IS 
       PORT (clk,interrupt  : IN  std_logic;
	     addr  : OUT   tw32;
	     data  : INOUT tw32);
END cpu;
  

ARCHITECTURE cpu_blk OF cpu IS
     SIGNAL  addr_bus,data_bus : tw32;
BEGIN
         ALU: BLOCK
              SIGNAL  ad_bus  : tw32;
         BEGIN
         …
         END BLOCK ALU;

         REG8:BLOCK
              SIGNAL  bidir_bus  : tw32;
         BEGIN
              REG1: BLOCK
                    SIGNAL  ad_bus  : tw32;
              BEGIN
              …
              END BLOCK REG1;
              …
              REG7: BLOCK
                    SIGNAL  ad_bus  : tw32;
              BEGIN
              …
              END BLOCK REG7;
         END BLOCK REG8;
         …
END cpu_blk;