mux2.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY mux2 IS 
           PORT (d0  : IN  std_logic_vector(3 DOWNTO 0);
                 d1  : IN  std_logic_vector(3 DOWNTO 0);
	         s   : IN  std_logic;
	         y   : OUT std_logic_vector(3 DOWNTO 0));
END mux2;

ARCHITECTURE rtl OF mux2 IS
         SIGNAL  tmp1,tmp2,tmp3  : std_logic_vector(3 DOWNTO 0);
BEGIN
         block1: BLOCK
         BEGIN
              tmp1(3) <= d0(3) AND s;
              tmp1(2) <= d0(2) AND s;
              tmp1(1) <= d0(1) AND s;
              tmp1(0) <= d0(0) AND s;
              tmp2(3) <= d1(3) AND (NOT s);
              tmp2(2) <= d1(2) AND (NOT s);
              tmp2(1) <= d1(1) AND (NOT s);
              tmp2(0) <= d1(0) AND (NOT s);
              tmp3 <= tmp1 OR tmp2;
              y <= tmp3;
         END BLOCK block1;
END rtl;