store_controller.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY store_controller IS 
           PORT (ready : IN  std_logic;
                 clk   : IN  std_logic;
                 read_write  : IN  std_logic;
		 we,oe       : OUT std_logic);
END store_controller;

ARCHITECTURE state_machine OF store_controller IS
     TYPE state_type IS (idle,decision,read,write);
     SIGNAL state  : state_type;
BEGIN
     state_transfer:PROCESS (clk)
     BEGIN
          IF (clk'event AND clk ='1') THEN
             CASE state IS
                  WHEN idle => we <= '0';	oe <= '0';
                               IF (ready ='1') THEN
                                   state <= decision;
                               ELSE
                                   state <= idle;
                               END IF;
                  WHEN decision => we <= '0';	oe <= '0';
                                   IF (read_write ='1') THEN
                                       state <= read;
                                   ELSE
                                       state <= write;
                                   END IF;
                  WHEN read => we <= '0';	oe <= '1';
                               IF (ready ='1') THEN
                                   state <= idle;
                               ELSE
                                   state <= read;
                               END IF;
                  WHEN write => we <= '1';	oe <= '0';
                                IF (ready ='1') THEN
                                    state <= idle;
                                ELSE
                                    state <= write;
                                END IF;
             END CASE;
          END IF;
     END PROCESS;
END state_machine;