store_controller.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY store_controller IS 
           PORT (ready : IN  std_logic;
                 clk   : IN  std_logic;
                 read_write  : IN  std_logic;
		 we,oe       : OUT std_logic);
END store_controller;

ARCHITECTURE state_machine OF store_controller IS
     TYPE state_type IS (idle,decision,read,write);
     SIGNAL present_state,next_state  : state_type;
BEGIN
     nextstate_logic:PROCESS (present_state,ready,read_write)
     BEGIN
          CASE present_state IS
               WHEN idle => IF (ready ='1') THEN
                                next_state <= decision;
                            ELSE
                                next_state <= idle;
                            END IF;
               WHEN decision => IF (read_write ='1') THEN
                                    next_state <= read;
                                ELSE
                                    next_state <= write;
                                END IF;
               WHEN read => IF (ready ='1') THEN
                                next_state <= idle;
                            ELSE
                                next_state <= read;
                            END IF;
               WHEN write => IF (ready ='1') THEN
                                next_state <= idle;
                             ELSE
                                next_state <= write;
                             END IF;
          END CASE;
     END PROCESS;
     
     state_transfer2:PROCESS (clk)
     VARIABLE present_state_tmp : state_type;
     BEGIN
          IF (clk'event AND clk ='1') THEN
              present_state_tmp := next_state;
              CASE present_state_tmp IS
                    WHEN idle     => we <= '0';	oe <= '0';
                    WHEN decision => we <= '0';	oe <= '0';
                    WHEN read     => we <= '0';	oe <= '1';
                    WHEN write    => we <= '1';	oe <= '0';
              END CASE;
          END IF;
          present_state <= present_state_tmp;
     END PROCESS;
END state_machine;