store_controller.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY store_controller IS 
           PORT (ready : IN  std_logic;
                 reset : IN  std_logic;
                 clk   : IN  std_logic;
                 read_write  : IN  std_logic;
		 we,oe       : OUT std_logic);
END store_controller;

ARCHITECTURE state_machine OF store_controller IS
     TYPE state_type IS (idle,decision,read,write);
     SIGNAL present_state,next_state  : state_type;
     SIGNAL oe_tmp,we_tmp : std_logic;
BEGIN
     state_transfer:PROCESS (reset,present_state,ready,read_write)
     BEGIN
          CASE present_state IS
               WHEN idle => IF (ready ='1') THEN
                                next_state <= decision;
                            ELSE
                                next_state <= idle;
                            END IF;
               WHEN decision => IF (read_write ='1') THEN
                                    next_state <= read;
                                ELSE
                                    next_state <= write;
                                END IF;
               WHEN read => IF (ready ='1') THEN
                                next_state <= idle;
                            ELSE
                                next_state <= read;
                            END IF;
               WHEN write => IF (ready ='1') THEN
                                next_state <= idle;
                             ELSE
                                next_state <= write;
                             END IF;
          END CASE;
     END PROCESS;
     oe_tmp <= '1' WHEN next_state = read  ELSE '0';
     we_tmp <= '1' WHEN next_state = write ELSE '0';
     state_register:PROCESS (clk,reset)
     BEGIN
          IF (reset ='1') THEN
              oe <= '0';
              we <= '0';
              present_state <= idle;
          ELSIF (clk'event AND clk ='1') THEN
              present_state <= next_state;
              oe <= oe_tmp;
              we <= we_tmp;
          END IF;
     END PROCESS;
END state_machine;